JAJSFM4A December 2018 – December 2018 LMK05318
PRODUCTION DATA.
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As long as all VDD core supplies are driven by the same 3.3-V supply rail that ramp in a monotonic manner from 0 V to 3.135 V, irrespective of the ramp time, then there is no requirement to add a capacitor on the PDN pin to externally delay the device power-up sequence. As shown in Figure 62, the PDN pin can be left floating or otherwise driven by a system host to meet the clock sequencing requirements in the system.