JAJSFM4A December 2018 – December 2018 LMK05318
PRODUCTION DATA.
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In APLL-only mode, the external XO input source determines the free-run frequency stability and accuracy of the output clocks. The BAW VCO1 determines the APLL1 output clock phase noise and jitter performance over the 12-kHz to 20-MHz integration band, regardless of the frequency and jitter of the XO input.
The principle of operation for APLL-only mode after power-on reset and initialization is as follows. If APLL2 is in cascaded mode as shown in Figure 26, VCO1 is held at its nominal center frequency of 2.5 GHz while APLL2 locks. Then APLL1 locks the VCO1 frequency to the external XO input and operates in free-run mode. The DPLL blocks are not used and do not affect the APLLs. VCO2 will track the VCO1 domain. Cascading APLL2 provides a high-frequency, ultra-low-jitter reference clock from VCO1 to minimize the APLL2 in-band phase noise/jitter impact that would occur otherwise if the APLL2's reference is from a XO/TCXO/OCXO with low frequency, high phase noise floor, or both.
If APLL2 is not cascaded as shown in Figure 25, VCO2 will lock to the XO input after initialization and operate independent of the DPLL/APLL1 domain.