JAJSFM4A December 2018 – December 2018 LMK05318
PRODUCTION DATA.
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Each reference input clock (PRIREF and SECREF) has its own 16-b reference divider to the DPLL TDC block. The R divider output of the selected reference sets the TDC input frequency. To support hitless switching between inputs with different frequencies, the R dividers can be used to divide the clocks to a single common frequency to the DPLL TDC input.