JAJSIA5 データシート

JAJSIA5D December 2019 – February 2022 LMK1C1102 , LMK1C1103 , LMK1C1104

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

DQF|8
- MPSS009B
PW|8
- MPDS568

サーマルパッド・メカニカル・データ

発注情報

7.5 Electrical Characteristics

VDD = 3.3 V ± 5 %, –40°C ≤ TA ≤ 125°C. Typical values are at VDD = 3.3 V, 25°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
CURRENT CONSUMPTION
I_DD	Core supply current, static	All-outputs disabled, f_IN = 0 V		25	45	µA
I_DD	Core supply current	All-outputs disabled, f_IN = 100 MHz		8	15	mA
		All-outputs active, f_IN = 100 MHz, C_L = 5pF, V_DD = 1.8 V		14	20
		All-outputs active, f_IN = 100 MHz, C_L = 5pF, V_DD = 2.5 V		21	30
		All-outputs active, f_IN = 100 MHz, C_L = 5pF, V_DD = 3.3 V		33	40
CLOCK INPUT
f_{IN_SE}	Input frequency	V_DD = 3.3 V	DC		250	MHz
f_{IN_SE}	Input frequency	V_DD = 2.5 V and 1.8 V	DC		200	MHz
V_IH	Input high voltage		0.7 x V_DD			V
V_IL	Input low voltage				0.3 x V_DD	V
dV_IN/dt	Input slew rate	20% - 80% of input swing	0.1			V/ns
I_{IN_LEAK}	Input leakage current		–50		50	uA
C_{IN_SE}	Input capacitance	at 25°C		7		pF
CLOCK OUTPUT FOR ALL V_DD LEVELS
f_OUT	Output frequency	V_DD = 3.3 V			250	MHz
f_OUT	Output frequency	V_DD = 2.5 V and 1.8 V			200	MHz
ODC	Output duty cycle	With 50% duty cycle input (for all VDD)	45		55	%
t_START	Start-up time before output is active	See ⁽¹⁾			3	ms
t_{1G_ON}	Output enable time	See ⁽²⁾			5	cycles
t_{1G_OFF}	Output disable time	See ⁽³⁾			5	cycles
CLOCK OUTPUT FOR V_DD = 3.3 V ± 5%
V_OH	Output high voltage	I_OH = 1 mA	2.8			V
V_OL	Output low voltage	I_OL = 1 mA			0.2	V
t_RISE-FALL	Output rise and fall time	20/80%, C_L= 5 pF, fIN = 156.25 MHz		0.35	0.7	ns
t_OUTPUT-SKEW	Output-output skew	See ⁽⁴⁾		25	50	ps
t_PART-SKEW	Part-to-part skew				250	ps
t_PROP-DELAY	Propagation delay	See ⁽⁵⁾		1.5	2	ns
t_JITTER-ADD	Additive Jitter	f_IN = 156.25 MHz, Input slew rate = 2 V/ns, Integration range = 12 kHz - 20 MHz		8	20	fs, RMS
R_OUT	Output impedance			50		Ω
CLOCK OUTPUT FOR V_DD = 2.5 V ± 5%
V_OH	Output high voltage	I_OH = 1 mA	0.8 x V_DD			V
V_OL	Output low voltage	I_OL = 1 mA			0.2 x V_DD	V
t_RISE-FALL	Output rise and fall time	20/80%, C_L= 5 pF, f_IN= 156.25 MHz		0.33	0.8	ns
t_OUTPUT-SKEW	Output-output skew	See ⁽⁴⁾			50	ps
t_PART-SKEW	Part-to-part skew				400	ps
t_PROP-DELAY	Propagation delay	See ⁽⁵⁾		1.5	2.5	ns
t_JITTER-ADD	Additive Jitter	f_IN = 156.25 MHz, Input slew rate = 2 V/ns, Integration range = 12 kHz - 20 MHz		11	27	fs, RMS
R_OUT	Output impedance			52.5		Ω
CLOCK OUTPUT FOR V_DD = 1.8 V ± 5%
V_OH	Output high voltage	I_OH = 1 mA	0.8 x V_DD			V
V_OL	Output low voltage	I_OL = 1 mA			0.2 x V_DD	V
t_RISE-FALL	Output rise and fall time	20/80%, C_L= 5 pF, f_IN= 156.25 MHz		0.38	1	ns
t_OUTPUT-SKEW	Output-output skew	See ⁽⁴⁾			50	ps
t_PART-SKEW	Part-to-part skew				900	ps
t_PROP-DELAY	Propagation delay	See ⁽⁵⁾		1.5	3	ns
t_JITTER-ADD	Additive Jitter	f_IN = 156.25 MHz, Input slew rate = 2 V/ns, Integration range = 12 kHz - 20 MHz		17.5	50	fs, RMS
R_OUT	Output impedance			60		Ω
GENERAL PURPOSE INPUT (1G)
V_IH	High-level input voltage		0.75 x V_DD			V
V_IL	Low-level input voltage				0.25 x V_DD	V
I_IH	Input high-level current	V_IH = V_{DD_REF}	–50		50	µA
I_IL	Input low-level current	V_IL = GND	–50		50	µA

(1) Measured from VDD stable to output active, when 1G = HIGH.

(2) Measured from 1G rising edge crossing VIH to first rising edge of Yn.

(3) Measured from 1G falling edge crossing VIL to last falling edge of Yn.

(4) Measured from rising edge of any Yn output to any other Ym output.

(5) Measured from rising edge of CLKIN to any Yn output.