JAJSIA5D December   2019  – February 2022 LMK1C1102 , LMK1C1103 , LMK1C1104

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fail-Safe Inputs
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 サポート・リソース
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

Figure 6-1 LMK1C1102 PW Package8-Pin TSSOPTop View
Figure 6-3 LMK1C1103 PW Package8-Pin TSSOPTop View
GUID-20210415-CA0I-8G5X-HRFX-6GNGNXMPRNC4-low.gif
  1. The DQF (WSON) package is equivalent to the DFN package of other vendors.
Figure 6-5 LMK1C1104 DQF Package8-Pin WSONTop View
  1. The DQF (WSON) package is equivalent to the DFN package of other vendors.
Figure 6-2 LMK1C1102 DQF Package8-Pin WSONTop View
Figure 6-4 LMK1C1104 PW Package8-Pin TSSOPTop View
Table 6-1 Pin Functions
PIN TYPE DESCRIPTION
NAME LMK1C
1102		 LMK1C
1103		 LMK1C
1104
LVCMOS CLOCK INPUT
CLKIN 1 1 1 Input Single-ended clock input with internal 300-kΩ (typical) pulldown resistor to GND. Typically connected to a single-ended clock input.
CLOCK OUTPUT ENABLE
1G 2 2 2 Input Global Output Enable with internal 300-kΩ (typical) pulldown resistor to GND. Typically connected to VDD with external pullup resistor.
HIGH: outputs enabled
LOW: outputs disabled
LVCMOS CLOCK OUTPUT
Y0 3 3 3 Output LVCMOS output. Typically connected to a receiver. Unused outputs can be left floating.
Y1 8 8 8
Y2 — 5 5
Y3 — — 7
SUPPLY VOLTAGE
VDD 6 6 6 Power Power supply terminal. Typically connected to a 3.3-V, 2.5-V, or 1.8-V supply. The VDD pin is typically connected to an external 0.1-μF capacitor near the pin.
GROUND
GND 4 4 4 GND Power supply ground.