JAJSJM9A December   2020  – January 2022 LMK1C1106 , LMK1C1108

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fail-Safe Inputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-20201001-CA0I-R9FW-DQXJ-2JR5HSZSSX0L-low.gifFigure 5-1 LMK1C1106 and LMK1C1108 PW Package14-Pin TSSOP and 16-Pin TSSOPTop View
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME LMK1C
1106		 LMK1C
1108
LVCMOS CLOCK INPUT
CLKIN 1 1 Input Single-ended clock input with internal 300-kΩ (typical) pulldown resistor to GND. Typically connected to a single-ended clock input.
CLOCK OUTPUT ENABLE
1G 2 2 Input Global Output Enable with internal 300-kΩ (typical) pulldown resistor to GND. Typically connected to VDD with external pullup resistor.
HIGH: outputs enabled
LOW: outputs disabled
LVCMOS CLOCK OUTPUT
Y0 3 3 Output LVCMOS output. Typically connected to a receiver. Unused outputs can be left floating.
Y1 14 16
Y2 11 13
Y3 13 15
Y4 6 6
Y5 9 11
Y6 – 8
Y7 – 9
SUPPLY VOLTAGE
VDD 5 5 Power Power supply terminal. Typically connected to a 3.3-V, 2.5-V, or 1.8-V supply. The VDD pin is typically connected to an external 0.1-μF capacitor near the pin.
8 10
12 14
GROUND
GND 4 4 GND Device ground.
7 7
10 12