JAJSJN5B december   2020  – june 2023 LMK1D1204 , LMK1D1208

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Electrical Characteristics
    5. 7.5 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fail-Safe Input and Hysteresis
      2. 9.3.2 Input Mux
    4. 9.4 Device Functional Modes
      1. 9.4.1 LVDS Output Termination
      2. 9.4.2 Input Termination
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.4.2 Input Termination

The LMK1D120x input stage is designed with flexibility in mind to allow the user to drive the device with a wide variety of signal types. This device can be interfaced with LVDS, LVPECL, LP-HCSL, HCSL, CML or LVCMOS drivers. Please refer to Electrical Characteristics for more details.

LVDS drivers can be connected to LMK1D120x inputs with DC- and AC-coupling as shown Figure 9-3 and Figure 9-4 (respectively).

GUID-38D910F7-AA80-4161-B606-04766B0A85A1-low.gifFigure 9-3 LVDS Clock Driver Connected to LMK1D120x Input (DC-Coupled)
GUID-DAB78B41-AC8C-4387-8594-C938C62ED031-low.gifFigure 9-4 LVDS Clock Driver Connected to LMK1D120x Input (AC-Coupled)

Figure 9-5 shows how to connect LVPECL inputs to the LMK1D120x. The series resistors are required to reduce the LVPECL signal swing if the signal swing is >1.6 VPP.

GUID-EAF11EF7-4D9B-48F9-B652-D2CCBFF4BA69-low.gifFigure 9-5 LVPECL Clock Driver Connected to LMK1D120x Input

Figure 9-6 illustrates how to couple a LVCMOS clock input to the LMK1D120x directly.

GUID-20201216-CA0I-HQGS-3Z57-5MXBHPGG3ZL8-low.gif Figure 9-6 1.8-V/2.5-V/3.3-V LVCMOS Clock Driver Connected to LMK1D120x Input

For unused input, TI recommends grounding both input pins (INP, INN) using 1-kΩ resistors.