JAJSMA9A october   2021  – june 2023 LMK1D1208P

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fail-Safe Input
    4. 9.4 Device Functional Modes
      1. 9.4.1 LVDS Output Termination
      2. 9.4.2 Input Termination
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Examples
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions


GUID-20211025-CA0I-STH3-HX5V-8KWHW57JHGQ5-low.svg
Figure 6-1 LMK1D1208P: RHA Package 40-Pin VQFN Top View
Table 6-1 Pin Functions
NAME NO. TYPE(1) DESCRIPTION
DIFFERENTIAL/SINGLE-ENDED CLOCK INPUT
IN0_P 8 I Primary: Differential input pair or single-ended input
IN0_N 9
IN1_P 2 I Secondary: Differential input pair or single-ended input.

Note that INP0, INN0 are used indistinguishably with IN0_P, IN0_N.
IN1_N 3
INPUT SELECT
IN_SEL 1 I Input selection with an internal 500-kΩ pullup and 320-kΩ pulldown, selects input port. See Table 9-2.
AMPLITUDE SELECT
AMP_SEL 10 I Output amplitude swing select with an internal 500-kΩ pullup and 320-kΩ pulldown. See Table 9-4.
OUTPUT ENABLE
OE0 6 I Output Enable for channel 0
HIGH (default): Enable output channel 0
LOW: Disable output channel 0 in Hi-Z state
OE1 16 I Output Enable for channel 1
HIGH (default): Enable output channel 1
LOW: Disable output channel 1 in Hi-Z state
OE2 17 I Output Enable for channel 2
HIGH (default): Enable output channel 2
LOW: Disable output channel 2 in Hi-Z state
OE3 18 I Output Enable for channel 3
HIGH (default): Enable output channel 3
LOW: Disable output channel 3 in Hi-Z state
OE4 33 I Output Enable for channel 4
HIGH (default): Enable output channel 4
LOW: Disable output channel 4 in Hi-Z state
OE5 34 I Output Enable for channel 5
HIGH (default): Enable output channel 5
LOW: Disable output channel 5 in Hi-Z state
OE6 35 I Output Enable for channel 6
HIGH (default): Enable output channel 6
LOW: Disable output channel 6 in Hi-Z state
OE7 5 I Output Enable for channel 7
HIGH (default): Enable output channel 7
LOW: Disable output channel 7 in Hi-Z state
BIAS VOLTAGE OUTPUT
VAC_REF0 4 O Bias voltage output for capacitive-coupled inputs. If used, TI recommends using a 0.1-µF capacitor to GND on this pin.
VAC_REF1 7
DIFFERENTIAL CLOCK OUTPUT
OUT0_P 12 O Differential LVDS output pair number 0
OUT0_N 13
OUT1_P 14 O Differential LVDS output pair number 1
OUT1_N 15
OUT2_P 22 O Differential LVDS output pair number 2
OUT2_N 23
OUT3_P 24 O Differential LVDS output pair number 3
OUT3_N 25
OUT4_P 26 O Differential LVDS output pair number 4
OUT4_N 27
OUT5_P 28 O Differential LVDS output pair number 5
OUT5_N 29
OUT6_P 36 O Differential LVDS output pair number 6
OUT6_N 37
OUT7_P 38 O Differential LVDS output pair number 7
OUT7_N 39
SUPPLY VOLTAGE
VDD 11, 20, 31, 40 P Device power supply (1.8 V, 2.5 V, or 3.3 V)
GROUND
GND 21, 30 G Ground
MISC
DAP DAP G Die Attach Pad. Connect to the printed circuit board (PCB) ground plane for heat dissipation.
NC 19, 32 — No Connection. Leave floating.
(1) G = Ground, I = Input, O = Output, P = Power