JAJSN77A october   2021  – april 2023 LMK1D1212 , LMK1D1216

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fail-Safe Input and Hysteresis
      2. 9.3.2 Input Mux
    4. 9.4 Device Functional Modes
      1. 9.4.1 LVDS Output Termination
      2. 9.4.2 Input Termination
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3 Feature Description

The LMK1D121x is a low additive jitter LVDS fan-out buffer that can generate up to 12 (LMK1D1212) or 16 (LMK1D1216) copies of two selectable LVPECL, LVDS, LP-HCSL, HCSL, or LVCMOS inputs. The LMK1D121x can accept reference clock frequencies up to 2 GHz while providing low output skew.

Table 9-2 lists the LMK1D1212 and LMK1D1216outputs divided into two banks.

Table 9-1 Output Bank
BankLMK1D1212LMK1D1216
0OUT0 to OUT5OUT0 to OUT7
1OUT6 to OUT11OUT8 to OUT15

Apart from providing a very low additive jitter and low output skew, the LMK1D121x has an input select pin (IN_SEL) and an output amplitude control pin (AMP_SEL).