JAJSMZ1B september   2021  – june 2023 LMK1D2102 , LMK1D2104

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fail-Safe Inputs
    4. 9.4 Device Functional Modes
      1. 9.4.1 LVDS Output Termination
      2. 9.4.2 Input Termination
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-20210513-CA0I-0CKC-FWLP-VNGR2BRR6RRH-low.svgFigure 6-1 LMK1D2102: RGT Package 16-Pin VQFN Top View
GUID-20210513-CA0I-T0HD-QF25-MGHVDHTQ7SFZ-low.svgFigure 6-2 LMK1D2104: RHD Package 28-Pin VQFN Top View
Table 6-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME LMK1D2102 LMK1D2104
DIFFERENTIAL/SINGLE-ENDED CLOCK INPUT
IN0_P, IN0_N 6, 7 9, 10 I Primary: Differential input pair or single-ended input
IN1_P, IN1_N 3, 4 5, 6 I Secondary: Differential input pair or single-ended input.
Note that INP0, INN0 are used indistinguishably with IN0_P, IN0_N.
OUTPUT BANK CONTROL
EN 2 4 I Output bank enable/disable with an internal 500-kΩ pullup and 320-kΩ pulldown, selects input port; (See Table 9-1)
BIAS VOLTAGE OUTPUT
VAC_REF0,VAC_REF1 8 11, 7 O Bias voltage output for capacitive coupled inputs. If used, TI recommends using a 0.1-µF capacitor to GND on this pin.
DIFFERENTIAL CLOCK OUTPUT
OUT0_P, OUT0_N 9, 10 12, 13 O Differential LVDS output pair number 0
OUT1_P, OUT1_N 11, 12 16, 17 O Differential LVDS output pair number 1
OUT2_P, OUT2_N 13, 14 18, 19 O Differential LVDS output pair number 2
OUT3_P, OUT3_N 15, 16 20, 21 O Differential LVDS output pair number 3
OUT4_P, OUT4_N 22, 23 O Differential LVDS output pair number 4
OUT5_P, OUT5_N 24, 25 O Differential LVDS output pair number 5
OUT6_P, OUT6_N 26, 27 O Differential LVDS output pair number 6
OUT7_P, OUT7_N 2, 3 O Differential LVDS output pair number 7
SUPPLY VOLTAGE
VDD 5 8, 15, 28 P Device Power Supply (1.8V or 2.5V or 3.3V)
GROUND
GND 1 1, 14 G Ground
DAP DAP DAP

G

 Die Attach Pad. Connect to the PCB ground plane for heat dissipation.
(1) G = Ground, I = Input, O = Output, P = Power