See Section 9.4.2 for proper input terminations, dependent on single-ended or differential inputs.

See Section 9.4.1 for output termination schemes depending on the receiver application.

TI recommends unused outputs to be terminated differentially with a 100-Ω resistor for optimum performance, although unterminated outputs are also okay but will result in slight degradation in performance (Output AC common-mode V_OS ) in the outputs being used.

In the application example described in the previous section Figure 10-2, the ADC clock and SYSREF clocks require different output interfacing schemes. Power supply filtering and bypassing is critical for low-noise applications.

In case of common-mode mismatch between the output voltage of the LMK1D210x and the receiver, one can use AC coupling to get around this, however, in certain applications, it might not be possible to AC couple the LMK1D210x outputs to the receiver due to the settling time associated with this AC coupling network (High-pass filter) which can result in non-deterministic behavior during the initial transients. For such applications, it becomes necessary to DC couple the outputs and thus requires a scheme which can overcome the inherent mismatch between the common-mode of the driver and receiver.

The application report Interfacing LVDS Driver With a Sub-LVDS Receiver discusses how to interface between a LVDS driver and sub-LVDS receiver. Same concept can be applied to interface the LMK1D210x outputs to a receiver which has lower common-mode.

Figure 10-2 Schematic for DC coupling LMK1D21xx with lower common-mode receiver

The Figure 10-2 illustrates the resistor divider network for stepping down the common mode as explained in the above application report. The resistors R1, R2 and R3 are chosen according to the input common mode requirements of the receiver. As highlighted before, user needs to make sure that the reduced swing is able to meet the requirements of the receiver.