JAJSN78A October 2021 – January 2022 LMK1D2106 , LMK1D2108
PRODUCTION DATA
- 1 特長
- 2 アプリケーション
- 3 概要
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ（パッケージ｜ピン）
- RHA|40
サーマルパッド・メカニカル・データ
- RHA|40
発注情報
7 Parameter Measurement Information
Figure 7-1 LVDS Output DC Configuration During Device TestFigure 7-2 LVDS Output AC Configuration During Device Test
Figure 7-3 DC-Coupled LVCMOS Input During Device Test
Figure 7-4 Output Voltage and Rise/Fall Time
Output skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2, ..7)
Part-to-part skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or the difference between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, ..7)
Figure 7-5 Output Skew and Part-to-Part Skew
Figure 7-6 Output Overshoot and Undershoot
Figure 7-7 Output AC Common Mode