The LMK1D210xL shown in Figure 9-1 is configured to fan-out an ADC clock on the first output bank and SYSREF clock on the second output bank for a system using the JESD204B/C ADC. The low output-to-output skew, very low additive jitter and superior spurious suppression between dual banks makes the LMK1D210xL a simple, robust and low-cost solution for distributing various clocks to JESD204B/C AFE systems. The configuration example can drive up to 2 to 8 ADC clocks and 2 to 8 SYSREF clocks for a JESD204B/C receiver with the following properties:

• The ADC clock receiver module is typically AC-coupled with an LVDS driver such as the LMK1D210xL due to differences in common-mode voltage between the driver and receiver. Depending on the receiver, there can an option for internal 100Ω differential termination in which case an external termination is not be required for the LMK1D210xL.
• The SYSREF clock receiver module is typically DC-coupled provided the common-mode voltage of the LMK1D210xL outputs match with the receiver. An external termination is not always necessary in case of an internal termination in the receiver.
• Unused outputs of the LMK1D210xL device are terminated differentially with a 100Ω resistor for optimum performance.