SNAS888A September   2024  – November 2024 LMK1D2102L , LMK1D2106L

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Output Common Mode
      2. 8.3.2 Fail-Safe Input
    4. 8.4 Device Functional Modes
      1. 8.4.1 Output Enable / Disable and Amplitude Selection
      2. 8.4.2 LVDS Output Termination
      3. 8.4.3 Input Termination
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RHA|40
サーマルパッド・メカニカル・データ
発注情報

7 Parameter Measurement Information

LMK1D2102L LMK1D2104L LMK1D2106L LMK1D2108L LVDS Output DC Configuration During Device TestFigure 7-1 LVDS Output DC Configuration During Device Test
LMK1D2102L LMK1D2104L LMK1D2106L LMK1D2108L LVDS Output AC Configuration During Device Test Figure 7-2 LVDS Output AC Configuration During Device Test
LMK1D2102L LMK1D2104L LMK1D2106L LMK1D2108L DC-Coupled LVCMOS Input During Device TestFigure 7-3 DC-Coupled LVCMOS Input During Device Test
LMK1D2102L LMK1D2104L LMK1D2106L LMK1D2108L Output Voltage and Rise/Fall TimeFigure 7-4 Output Voltage and Rise/Fall Time
LMK1D2102L LMK1D2104L LMK1D2106L LMK1D2108L Output Skew and Part-to-Part Skew
A. Output skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2, ..N)
B. Part-to-part skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or the difference between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, ..N)
Figure 7-5 Output Skew and Part-to-Part Skew
LMK1D2102L LMK1D2104L LMK1D2106L LMK1D2108L Output Overshoot and UndershootFigure 7-6 Output Overshoot and Undershoot
LMK1D2102L LMK1D2104L LMK1D2106L LMK1D2108L Output AC Common ModeFigure 7-7 Output AC Common Mode