SNAS888A September   2024  – November 2024 LMK1D2102L , LMK1D2106L

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Output Common Mode
      2. 8.3.2 Fail-Safe Input
    4. 8.4 Device Functional Modes
      1. 8.4.1 Output Enable / Disable and Amplitude Selection
      2. 8.4.2 LVDS Output Termination
      3. 8.4.3 Input Termination
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RHA|40
サーマルパッド・メカニカル・データ
発注情報

3 Description

The LMK1D210xL is a low noise dual clock buffer which distributes one input to a maximum of 2 (LMK1D2102L), 4 (LMK1D2104L), 6 (LMK1D2106L) or 8 (LMK1D2108L) LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML, or LVCMOS.

The LMK1D210xL is specifically designed for driving 50Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin (see Figure 8-8).

LMK1D210xL buffer offers two output common mode operation (0.7V and 1.2V) for different operating supply. The device provides flexibility in design for DC-coupled mode applications.

AMP_SELA / AMP_SELB control pin can be used to select different output amplitude LVDS (350mV) or boosted LVDS (500mV). In addition to amplitude selection, outputs can be disabled using the same pin.

The part also supports Fail-Safe Input function for clock and digital input pins. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

Package Information
PART NUMBER(1) PACKAGE PACKAGE SIZE(3)
LMK1D2102LRGT (VQFN, 16)3.00mm × 3.00mm
LMK1D2104LRHD (VQFN, 28)5.00mm × 5.00mm
LMK1D2106L RHA (VQFN, 40) 6.00mm × 6.00mm
LMK1D2108L(2) RGZ (VQFN, 48) 7.00mm × 7.00mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
(2) Preview only.
(3) The package size (length × width) is a nominal value and includes pins, where applicable.
LMK1D2102L LMK1D2104L LMK1D2106L LMK1D2108L Application Example Application Example