SNAS888A September   2024  – November 2024 LMK1D2102L , LMK1D2106L

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Output Common Mode
      2. 8.3.2 Fail-Safe Input
    4. 8.4 Device Functional Modes
      1. 8.4.1 Output Enable / Disable and Amplitude Selection
      2. 8.4.2 LVDS Output Termination
      3. 8.4.3 Input Termination
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

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発注情報

6.5 Electrical Characteristics

VDD = 1.8V, 2.5V, 3.3V ± 5%, –40°C ≤ TA ≤ 105°C. Typical values are at VDD = 1.8V, 2.5V, 3.3V, 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY CHARACTERISTICS
IDD100M LMK1D2102L All-outputs enabled, RL = 100Ω, f =100MHz, AMP_SELA = 0 70 80 mA
IDD100M LMK1D2104L All-outputs enabled, RL = 100Ω, f =100MHz, AMP_SELA = 0 80 105 mA
IDD100M LMK1D2106L All-outputs enabled, RL = 100Ω, f =100MHz, AMP_SELA and AMP_SELB = 0 113 140 mA
IDD100M LMK1D2108L All-outputs enabled, RL = 100Ω, f =100MHz, AMP_SELA and AMP_SELB = 0 134 160 mA
IDD100M LMK1D2102L All-outputs enabled, RL = 100Ω, f =100MHz, AMP_SELA = Float 75 87 mA
IDD100M LMK1D2104L All-outputs enabled, RL = 100Ω, f =100MHz, AMP_SELA = Float 85 115 mA
IDD100M LMK1D2106L All-outputs enabled, RL = 100Ω, f =100MHz, AMP_SELA and AMP_SELB = Float 134 160 mA
IDD100M LMK1D2108L All-outputs enabled, RL = 100Ω, f =100MHz, AMP_SELA and AMP_SELB = Float 155 180 mA
IDDPOWER DOWN LMK1D2102L All-outputs disabled and unterminated, AMP_SELA = 1 50 mA
IDDPOWER DOWN LMK1D2102L All-outputs disabled, RL = 100Ω, AMP_SELA = 1 65 mA
IDDPOWER DOWN LMK1D2104L All-outputs disabled and unterminated, AMP_SELA = 1 55 mA
IDDPOWER DOWN LMK1D2104L All-outputs disabled, RL = 100Ω, AMP_SELA = 1 80 mA
IDDPOWER DOWN LMK1D2106L All-outputs disabled and unterminated, AMP_SELA and AMP_SELB = 1 75 mA
IDDPOWER DOWN LMK1D2106L All-outputs disabled, RL = 100Ω, AMP_SELA and AMP_SELB = 1 110 mA
IDDPOWER DOWN LMK1D2108L All-outputs disabled and unterminated, AMP_SELA and AMP_SELB = 1 80 mA
IDDPOWER DOWN LMK1D2108L All-outputs disabled, RL = 100Ω, AMP_SELA and AMP_SELB = 1 130 mA
 AMP_SELA / AMP_SELB INPUT CHARACTERISTICS 
VdI3 3-state input Open / floating 0.4*VCC V
VIH Input high voltage Minimum input voltage for a logical "1" state 0.7*VCC VCC + 0.3 V
VIL Input low voltage Maximum input voltage for a logical "0" state –0.3 0.3*VCC V
IIH Input high current VDD can be 1.8V/2.5V/3.3V with VIH = VDD 30 µA
IIL Input low current VDD can be 1.8V/2.5V/3.3V with VIH = VDD –30 µA
Rpull-up Input pullup resistor (AMP_SELA, AMP_SELB) 500 kΩ
Rpull-down Input pulldown resistor (AMP_SELA, AMP_SELB) 320 kΩ
SINGLE-ENDED LVCMOS/LVTTL CLOCK INPUT 
fIN Input frequency Clock input DC 250 MHz
VIN_S-E Single-ended Input Voltage Swing Assumes a square wave input with two levels 0.4 3.465 VPP
dVIN/dt Input Slew Rate (20% to 80% of the amplitude) 0.05 V/ns
IIH Input high current VDD = 3.465V, VIH = 3.465V 50 µA
IIL Input low current VDD = 3.465V, VIL = 0V -30 µA
CIN_SE Input capacitance at 25°C 3.5 pF
DIFFERENTIAL CLOCK INPUT 
fIN Input frequency Clock input 2 GHz
VIN,DIFF(p-p) Differential input voltage peak-to-peak {2*(VINP-VINN)} VICM = 1V (VDD = 1.8V) 0.3 2.4 VPP
VICM = 1.25V (VDD = 2.5V/3.3V) 0.3 2.4
VICM Input common mode voltage VIN,DIFF(P-P) > 0.4V (VDD = 1.8V/2.5V/3.3V) 0.25 2.3 V
IIH Input high current VDD = 3.465V, VINP = 2.4V, VINN = 1.2V 30 µA
IIL Input low current VDD = 3.465 V, VINP = 0V, VINN = 1.2V –30 µA
CIN_S-E Input capacitance (Single-ended) at 25°C 3.5  pF
LVDS DC OUTPUT CHARACTERISTICS
|VOD| Differential output voltage magnitude |VOUTP - VOUTN| VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, AMP_SELA, AMP_SELB = 0 250 350 450 mV
|VOD| Differential output voltage magnitude |VOUTP - VOUTN| VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, AMP_SELA, AMP_SELB = Float 400 500 650 mV
ΔVOD Change in differential output voltage magnitude. Per output, defined as the difference between VOD in logic hi/lo states. VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, AMP_SELA, AMP_SELB = 0 –15 15 mV
ΔVOD Change in differential output voltage magnitude VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, AMP_SELA, AMP_SELB = Float –20 20 mV
VOC(SS) Steady-state common mode output voltage VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, VDD = 1.8V, AMP_SELA, AMP_SELB = 0 0.6 0.7 0.8 V
VOC(SS) Steady-state common mode output voltage (LMK1D2104L, LMK1D2106L, LMK1D2108L) VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, VDD = 1.8V, AMP_SELA, AMP_SELB = Float 0.6 0.7 0.8 V
VOC(SS) Steady-state common mode output voltage (LMK1D2102L) VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, VDD = 1.8V, AMP_SELA, AMP_SELB = Float, TA = -40℃ to 105℃ 0.6 0.7 0.82 V
VOC(SS) Steady-state common mode output voltage (LMK1D2102L) VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, VDD = 1.8V, AMP_SELA, AMP_SELB = Float, TA = -40℃ to 85℃ 0.6 0.7 0.8 V
VOC(SS) Steady-state common mode output voltage VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, VDD = 2.5V/3.3V, AMP_SELA, AMP_SELB = 0 1.1 1.375 V
VOC(SS) Steady-state common mode output voltage VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, VDD = 2.5V/3.3V, AMP_SELA, AMP_SELB = Float 0.9 1.15 V
ΔVOC(SS) Change in steady-state common mode output voltage VIN,DIFF(P-P) =  0.3VPP, RL = 100Ω, AMP_SELA, AMP_SELB = 0 –15 -15 mV
ΔVOC(SS) Change in steady-state common mode output voltage VIN,DIFF(P-P) =  0.3VPP, RL = 100Ω, AMP_SELA, AMP_SELB = Float –20 20 mV
LVDS AC OUTPUT CHARACTERISTICS
Vring Output overshoot and undershoot VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, fOUT ≤ 491.52MHz –0.1 0.1 VOD
VOS Output AC common mode VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, AMP_SELA, AMP_SELB = 0 50 100 mVpp
VOS Output AC common mode VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, AMP_SELA, AMP_SELB = Float 75 150 mVpp
VOS Output AC common mode VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω  50 100 mVpp
IOS Short-circuit output current (differential) VOUTP = VOUTN –12 12 mA
IOS(cm) Short-circuit output current (common-mode) VOUTP = VOUTN = 0 –24 24 mA
tPD Propagation delay VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω (1) 0.3 0.575 ns
tSK, O Output skew Skew between outputs with the same load conditions 20 ps
tSK, b Output bank skew Skew between the outputs within the same bank (2102L/2104L) (2) 15 ps
tSK, b Output bank skew skew between the outputs within the same bank (2106L/2108L) (2) 17.5 ps
tSK, PP Part-to-part skew Skew between outputs on different parts subjected to the same operating conditions with the same input and output loading. 150 ps
tSK, P Pulse skew 50% duty cycle input, crossing point-to-crossing-point distortion (2) –20 20 ps
tRJIT(ADD) Random additive Jitter (rms) fIN = 156.25MHz with 50% duty-cycle, Input slew rate = 1.5V/ns, Integration range = 12kHz - 20MHz, with output load RL = 100Ω  45 60 fs, RMS
Phase noise Phase Noise for a carrier frequency of 156.25MHz with 50% duty-cycle, Input slew rate = 1.5V/ns with output load RL= 100Ω PN1kHz  –143 dBc/Hz
PN10kHz  -152
PN100kHz -157
PN1MHz  -160
PNfloor  –164
MUXISO Mux Isolation fIN = 156.25MHz. The difference in power level at fIN when the selected clock is active and the unselected clock is static versus when the selected clock is inactive and the unselected clock is active. 80 dB
SPUR Spurious suppression between dual banks Differential inputs with FIN0 = 491.52MHz, FIN1 = 61.44MHz; Measured between neighboring outputs –60 dB
Different inputs with FIN0 = 491.52MHz, FIN1 = 15.36MHz; Measured between neighboring outputs –70
ODC Output duty cycle With 50% duty cycle input 45 55 %
tR/tF Output rise and fall time 20% to 80% with RL = 100Ω 300 ps
VAC_REF Reference output voltage VDD = 2.5V, ILOAD = 100µA 0.9 1.25 1.375 V
POWER SUPPLY NOISE REJECTION (PSNR) VDD = 2.5V / 3.3V
PSNR Power Supply Noise Rejection (fcarrier = 156.25MHz) 10kHz, 100mVpp ripple injected on VDD –95 dBc
1MHz, 100mVpp ripple injected on VDD –75
(1) Measured between single-ended/differential input crossing point to the differential output crossing point.
(2) Defined as the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.