JAJSN78A October   2021  – January 2022 LMK1D2106 , LMK1D2108

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fail-Safe Input
    4. 8.4 Device Functional Modes
      1. 8.4.1 LVDS Output Termination
      2. 8.4.2 Input Termination
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions



Figure 5-1 LMK1D2106: RHA Package 40-Pin VQFN Top View


Figure 5-2 LMK1D2108: RGZ Package 48-Pin VQFN Top View
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME LMK1D2106 LMK1D2108
DIFFERENTIAL/SINGLE-ENDED CLOCK INPUT
IN0_P, IN0_N 8, 9 9, 10 I Primary: Differential input pair or single-ended input
IN1_P, IN1_N 2, 3 3, 4 I Secondary: Differential input pair or single-ended input
Note that INP0, INN0 are used indistinguishably with IN0_P, IN0_N.
BANK ENABLE
EN 1 2 I Output bank enable/disable with an internal 500-kΩ pullup and 320-kΩ pulldown. See Table 8-2.
AMPLITUDE SELECT
AMP_SEL 10 11 I Output amplitude swing select with an internal 500-kΩ pullup and 320-kΩ pulldown. See Table 8-3.
BIAS VOLTAGE OUTPUT
VAC_REF0,VAC_REF1 7, 4 8, 5 O Bias voltage output for capacitive coupled inputs. If used, TI recommends using a 0.1-µF capacitor to GND on this pin.
DIFFERENTIAL CLOCK OUTPUT
OUT0_P, OUT0_N 12, 13 14, 15 O Differential LVDS output pair number 0
OUT1_P, OUT1_N 14, 15 16, 17 O Differential LVDS output pair number 1
OUT2_P, OUT2_N 16, 17 18, 19 O Differential LVDS output pair number 2
OUT3_P, OUT3_N 18, 19 20, 21 O Differential LVDS output pair number 3
OUT4_P, OUT4_N 22, 23 22, 23 O Differential LVDS output pair number 4
OUT5_P, OUT5_N 24, 25 25, 26 O Differential LVDS output pair number 5
OUT6_P, OUT6_N 26, 27 27, 28 O Differential LVDS output pair number 6
OUT7_P, OUT7_N 28, 29 29, 30 O Differential LVDS output pair number 7
OUT8_P, OUT8_N 32, 33 31, 32 O Differential LVDS output pair number 8
OUT9_P, OUT9_N 34, 35 33, 34 O Differential LVDS output pair number 9
OUT10_P, OUT10_N 36, 37 35, 36 O Differential LVDS output pair number 10
OUT11_P, OUT11_N 38, 39 38, 39 O Differential LVDS output pair number 11
OUT12_P, OUT12_N — 40, 41 O Differential LVDS output pair number 12
OUT13_P, OUT13_N — 42, 43 O Differential LVDS output pair number 13
OUT14_P, OUT14_N — 44, 45 O Differential LVDS output pair number 14
OUT15_P, OUT15_N — 46, 47 O Differential LVDS output pair number 15
SUPPLY VOLTAGE
VDDA 6, 11, 20 7, 13, 24 P Device power supply (1.8 V, 2.5 V, or 3.3 V) for Bank 0
VDDB 5, 31, 40 6, 37, 48 P Device power supply (1.8 V, 2.5 V, or 3.3 V) for Bank 1
GROUND
GND 21, 30 1, 12 G Ground
MISC
DAP DAP DAP G Die Attach Pad. Connect to the printed circuit board (PCB) ground plane for heat dissipation.
(1) G = Ground, I = Input, O = Output, P = Power