See Section 8.4.2 for proper input terminations, dependent on single-ended or differential inputs.

See Section 8.4.1 for output termination schemes depending on the receiver application.

TI recommends unused outputs to be terminated differentially with a 100-Ω resistor for optimum performance, although unterminated outputs are also okay but will result in slight degradation in performance (Output AC common-mode V_OS) in the outputs being used.

In this application example, the ADC clock and SYSREF clocks require different output interfacing schemes. Power-supply filtering and bypassing is critical for low-noise applications.

In case of common-mode mismatch between the output voltage of the LMK1D210x and the receiver, one can use AC coupling to get around this. It might not be possible in certain applications, however, to AC-couple the LMK1D210x outputs to the receiver due to the settling time associated with this AC-coupling network (High-pass filter), which can result in non-deterministic behavior during the initial transients. For such applications, DC-coupling the outputs is necessary and thus requires a scheme which can overcome the inherent mismatch between the common-mode voltage of the driver and receiver.

The application report Interfacing LVDS Driver With a Sub-LVDS Receiver discusses how to interface between a LVDS driver and sub-LVDS receiver. The same concept can be applied to interface the LMK1D210x outputs to a receiver which has a lower common-mode voltage.

Figure 9-2 shows the resistor divider network for stepping down the common-mode voltage as explained in the above application report. The resistors R1, R2 and R3 are chosen according to the input common-mode voltage requirements of the receiver. As highlighted before, make sure that the reduced swing is able to meet the requirements of the receiver. Higher swing mode (boosted LVDS swing mode) can be selected using the AMP_SEL pin highlighted in Table 8-3 to compensate for the reduced swing as the result of the resistor voltage divider.