JAJSJO2B March 2022 – July 2022 LMK5B33216
PRODUCTION DATA
As long as all VDD and VDDO supplies are driven by the same 3.3-V supply rail that ramp in a monotonic manner from 0 V to 3.135 V, and the time between decision point 2 and stabilized supply voltage is less than 1 ms, then there is no requirement to add a capacitor on the PD# pin to externally delay the device power-up sequence. Figure 9-1 shows that the PD# pin can be left floating or otherwise driven by a system host to meet the clock sequencing requirements in the system.
If time between decision point 2 and stabilized supply voltage is greater than 1 ms, then the PD# pin must be delayed. Refer to Section 9.1.6.3.
As described in Section 9.1.7, it is necessary for the XO reference to be valid after PD# decision point 1 to ensure successful VCO1 and VCO2 calibration.