JAJSJO2C March 2022 – February 2025 LMK5B33216
PRODUCTION DATA
The APLL fractional N divider includes a 12-bit integer portion (INT), a 40-b numerator portion (NUM), a fixed 40-bit or a programmable 24-bit denominator portion (DEN), and an SDM. The INT and NUM are programmable. When an APLL works with a DPLL in a loop, the APLL uses a fixed 40-bit denominator for very high frequency resolution on the VCO clock. When the APLL works in an independent loop (the paired DPLL is disabled), TI recommends a 24-bit programmable denominator. The total APLL N divider value is: N = INT + NUM / 240 or INT + NUM / 224.
In APLL free-run mode, the PFD frequency and total N divider for the APLL determine the VCO frequency, which can be computed with 24-bit denominator by Equation 2.