JAJSN00A September 2022 – February 2025 LMK5B33414
PRODUCTION DATA
The LMK5B33414 can support system reference clocks from 1PPS to 25MHz including JEDEC JESD204B or JESD204C SYSREF clocks. Any 12-bit output channel divider (except OUT2 and OUT3) can be cascaded with an individual 20-bit SYSREF divider. Set flexible SYSREF divider values to generate the same SYSREF/1PPS frequency on multiple outputs or different frequency multiples of SYSREF/1PPS based on application requirements. When aligning multiple SYSREF outputs, set SYSREF_REQ_MODE 0x1A[5:4] = 11 for resampling of the SYSREF request. The SYSREF/1PPS can also be replicated on GPIO1 or GPIO2 if additional single ended outputs are needed. The SYSREF request sample source SYSREF_REQ_SEL 0x1A[3:2] must be set to the same source as desired for SYSREF/1PPS output replication.
The SYSREF divider output signals can be replicated on either GPIO1 and GPIO2 to provide additional single ended 3.3V CMOS clocks after start-up if desired. To configure the SYSREF/1PPS output replication the GPIO must be enabled as an output (GPIOx_OUTEN = 1) and one of the SYSREF output to GPIO replication sources must be active. The SYSREF replication source comes from any one of the enabled SYSREF dividers used by or OUT12/13 by register programming (OUT_x_y_SR_GPIO_EN = 1). The GPIOx replicated SYSREF output is after static digital delay but before the analog and digital delay and pulser. The output is a continuous frequency as pulsed SYSREF mode is not supported for the GPIOx replica.
There is some small fixed delay skew between the normal SYSREF and GPIO replicated SYSREF. An LVCMOS output clock is an unbalanced signal with large voltage swing; therefore, the signal can strongly interfere and couple noise onto other jitter-sensitive differential output clocks.