Figure 7-10 through Figure 7-13 show the recommended input interfacing and termination circuits. Unused clock
inputs can be left floating or pulled down.
Figure 7-10 Single-Ended LVCMOS (1.8 V, 2.5 V, 3.3 V) to Reference (INx_P) or XO Input (XO)
Figure 7-11 DC-Coupled LVPECL to Reference (INx)
Figure 7-12 DC-Coupled HSDS/LVDS to Reference (INx)
Figure 7-13 HCSL (Load Terminated) to Reference (INx)