JAJSP85 December 2023 LMK5C33216A
PRODUCTION DATA
APLL3 supports a programmable loop bandwidth from 100 Hz to 10 kHz (typical range), and APLL1 or APLL2 supports a programmable loop bandwidth from 100 kHz to 1 MHz (typical range). The loop filter components can be programmed to optimize the APLL bandwidth depending on the reference input frequency and phase noise. The LF1, LF2, and LF3 pins each require an external C2 capacitor to ground. See the suggested values for the LF1, LF2, and LF3 capacitors in Pin Configuration and Functions.
Figure 7-22 shows the APLL loop filter structure between the PFD/charge pump output and VCO control input.