When TEC_CNTR_TRIG is 1 (GPIO pin):
- Timing accuracy of 1 TEC cycle + 2 ns requires a
20% to 80% rise time of less than or equal to 1
ns.
- GPIOx rising edge should not occur within 10 ns
of rising SCS which sets TEC_CNTR_EN from 0 to
1.
- GPIOx should remain high for 10 ns.
- A new GPIOx trigger should not arrive within 1 µs
of the rising edge of the SPI SCS after reading
the LSB of the TEC_CNTR.
When TEC_CNTR_TRIG is 0 (SPI):
- Timing accuracy of 1 TEC cycle + 2 ns requires an
80% to 20% fall time of less than or equal to 1
ns.
- The TEC counter is captured to the TEC_CNTR
registers at the falling edge of SPI SCS. No
additional time to read back or pre-latching of
register is required.