JAJSE94B december 2017 – august 2023 LMK61E07
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
The PLL_MASHCTRL register provides control of the fractional divider for PLL.
BIT NO. | FIELD | TYPE | DEFAULT | EEPROM | DESCRIPTION | |
---|---|---|---|---|---|---|
[7:4] | RESERVED | - | - | N |
Reserved. | |
[3:2] | PLL_DTHRMODE[1:0] | RW | 0x3 | Y |
Mash Engine dither mode control. | |
DITHERMODE | Dither Configuration | |||||
0 (0x0) | Weak | |||||
1 (0x1) | Reserved | |||||
2 (0x2) | Reserved | |||||
3 (0x3) | Dither Disabled | |||||
[1:0] | PLL_ORDER[1:0] | RW | 0x0 | Y |
Mash Engine Order. | |
ORDER | Order Configuration | |||||
0 (0x0) | Integer Mode Divider | |||||
1 (0x1) | Reserved | |||||
2 (0x2) | Reserved | |||||
3 (0x3) | 3rd order |