9.2.2 Detailed Design Procedure

This design procedure will give a quick outline of the process of configuring the LMK61E0M in the above use case. Typically, the easiest approach to configuring the PLL is to start with the desired output frequency and work backwards.

1. VCO Frequency Selection
   • The first step is to calculate the possible VCO frequencies given the required output frequency of 70.656 MHz. The LMK61E0M output dividers consist of the VCO post divider that can be set to /4 or /5, and the output divider that can be set from /6 to /256. The VCO can output frequencies from 4.6 GHz to 5.6 GHz. Therefore, the output frequency multiplied by the total divide value must fall within this range.
   • To determine the boundary of the total divide value, we can divide the VCO frequency limits by the output frequency, resulting in a range of 65.1 to 79.3. Any combination of dividers that result in a total divide value within this range will result in a valid VCO frequency. The possible divider combinations and the resulting VCO frequencies are listed in columns 1 and 2, respectively, of Table 4, below.
2. Input Divider and Doubler/Phase Detector Frequency Configuration
   • The next step is to set the reference divider and doubler in the reference frequency path to the PLL. The reference divider can be set to /1 or /4, and the doubler can be set to x1 or x2. The main trade-off is that a higher phase detector frequency will result in better output phase noise performance and a lower phase detector frequency will result in a finer output frequency step size when adjusting the feedback divider numerator in DCXO mode.
   • In the DSL application, a finer step size is desired so the reference divider will be set to /4 and the doubler to x1 to minimize the phase detector frequency. The phase detector frequency can then be calculated by multiplying and dividing the reference frequency of 50 MHz by those values, resulting in 12.5 MHz.
   • Note that in some applications, a trade-off in step size to obtain better phase noise performance is acceptable. In that case the design procedure can be continued, substituting the relevant reference divider and doubler configuration and phase detector frequency.
3. Feedback Divider Selection
   • The possible feedback divider values can then be calculated by dividing the VCO frequency by the phase detector frequency. The possible values are listed in column 3 of Table 4.
   • Glitch-less frequency margining in DCXO mode is achieved by adjusting the numerator of the feedback divider without changing the integer value of the divider, which could cause a frequency glitch. Therefore, the output frequency tuning range is limited by which VCO frequency and feedback divider we select out of the valid combinations. To obtain as equal of a tuning range above and below the nominal output frequency as possible, a feedback divider value with fractional portion as close to 1/2 as possible should be chosen.
   • The VCO frequency of 5369.856 MHz results in a feedback divider of 429.58848, which has a fractional portion closest to 1/2. The decimal converted to a fraction is 429+58848/100000. To minimize step size, the fraction can be converted to the maximum equivalent fraction of 2412768/4100000 as limited by the maximum denominator of 4194303.
4. Frequency Margining
   • With the device configured to output the nominal frequency of 70.656 MHz, the numerator can be adjusted over I²C to tune the output frequency.
   • Using equation 3 in Configuring the PLL, the step size of this configuration can be calculated to be approximately 4x10^–8 MHz or 0.58 ppb.
   • The maximum and minimum tuning range limits can be determined by calculating the maximum shift in frequency from nominal without changing the integer portion of the feedback divider (including setting the numerator to zero or equal to the denominator). In this case, the limits are a maximum of +955 ppm and a minimum of –1365 ppm from nominal.