JAJSKX8C December   2020  – March 2022 LMP7704-SP

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: VS = 5 V
    6. 6.6 Electrical Characteristics: VS = 10 V
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Radiation Hardened Performance
      2. 7.3.2 Engineering Model (Devices With /EM Suffix)
      3. 7.3.3 Capacitive Load
      4. 7.3.4 Input Capacitance
      5. 7.3.5 Diodes Between the Inputs
    4. 7.4 Device Functional Modes
      1. 7.4.1 Precision Current Source
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Low Input Voltage Noise
      2. 8.1.2 Total Noise Contribution
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.3 Capacitive Load

The LMP7704-SP can be connected as a noninverting unity gain follower. This configuration is the most sensitive to capacitive loading.

The combination of a capacitive load placed on the output of an amplifier along with the amplifier output impedance creates a phase lag, which in turn reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the response is either underdamped or oscillated.

To drive heavier capacitive loads, use an isolation resistor, labeled as RISO in Figure 7-1. By using this isolation resistor, the capacitive load is isolated from the amplifier output, and thus, the pole caused by CL is no longer in the feedback loop. The larger the value of RISO, the more stable the output voltage. If values of RISO are sufficiently large, the feedback loop will be stable, independent of the value of CL. However, larger values of RISO result in reduced output swing and reduced output current drive.

GUID-AA93FD8F-269B-4F99-BAA1-8C7496519819-low.pngFigure 7-1 Isolating Capacitive Load