SNAS521H July   2011  – January 2016 LMP90077 , LMP90078 , LMP90079 , LMP90080

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Timing Requirements
    7. 8.7  Timing Requirements - CSB Timing
    8. 8.8  Timing Requirements - SCLK and SDI Timing
    9. 8.9  Timing Requirements - SDO Timing With DOD1
    10. 8.10 Timing Requirements - SDO Timing with DOD2
    11. 8.11 Timing Requirements - SDO and DRDYB Timing
    12. 8.12 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Calibration
        1. 9.3.1.1 Background Calibration
          1. 9.3.1.1.1 Types of Background Calibration:
          2. 9.3.1.1.2 Using Background Calibration:
        2. 9.3.1.2 System Calibration
          1. 9.3.1.2.1 System Calibration Offset Coefficient Determination Mode
          2. 9.3.1.2.2 System Calibration Gain Coefficient Determination Mode
          3. 9.3.1.2.3 Post-Calibration Scaling
      2. 9.3.2 True Continuous Background Calibration
      3. 9.3.3 Continuous Background Sensor Diagnostics
      4. 9.3.4 Flexible Input MUX Channels
      5. 9.3.5 Programmable Gain Amplifiers (FGA & PGA)
      6. 9.3.6 Excitation Current Sources (IB1 & IB2) - LMP90080/LMP90078
      7. 9.3.7 Signal Path
        1. 9.3.7.1 Reference Input (VREF)
        2. 9.3.7.2 Flexible Input MUX (VIN)
        3. 9.3.7.3 Selectable Gains (FGA and PGA)
        4. 9.3.7.4 Buffer (BUFF)
        5. 9.3.7.5 Internal/External CLK Selection
        6. 9.3.7.6 Programmable ODRS
        7. 9.3.7.7 Digital Filter
        8. 9.3.7.8 GPIO (D0-D6)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Channels Scan Mode
        1. 9.4.1.1 ScanMode0: Single-Channel Continuous Conversion
        2. 9.4.1.2 ScanMode1: Multiple-Channels Single Scan
        3. 9.4.1.3 ScanMode2: Multiple-Channels Continuous Scan
        4. 9.4.1.4 ScanMode3: Multiple-Channels Continuous Scan with Burnout Currents
      2. 9.4.2 Sensor Interface
        1. 9.4.2.1 IB1 & IB2 - Excitation Currents (LMP90080/LMP90078)
        2. 9.4.2.2 Burnout Currents
          1. 9.4.2.2.1 Burnout Current Injection
        3. 9.4.2.3 Sensor Diagnostic Flags
          1. 9.4.2.3.1 SHORT_THLD_FLAG
          2. 9.4.2.3.2 RAILS_FLAG
          3. 9.4.2.3.3 POR_AFT_LST_RD
          4. 9.4.2.3.4 OFLO_FLAGS
          5. 9.4.2.3.5 SAMPLED_CH
    5. 9.5 Programming
      1. 9.5.1 Serial Digital Interface
        1. 9.5.1.1 Register Address (ADDR)
        2. 9.5.1.2 Register Read/Write Protocol
        3. 9.5.1.3 Streaming
        4. 9.5.1.4 CSB - Chip Select Bar
        5. 9.5.1.5 SPI Reset
        6. 9.5.1.6 DRDYB - Data Ready Bar
          1. 9.5.1.6.1 DrdybCase1: Combining SDO/DRDYB with SDO_DRDYB_DRIVER = 0x00
          2. 9.5.1.6.2 DrdybCase2: Combining SDO/DRDYB with SDO_DRDYB_DRIVER = 0x03
          3. 9.5.1.6.3 DrdybCase3: Routing DRDYB to D6
        7. 9.5.1.7 Data Only Read Transaction
        8. 9.5.1.8 Cyclic Redundancy Check (CRC)
      2. 9.5.2 RESET and RESTART
      3. 9.5.3 Register Read/Write Examples
        1. 9.5.3.1 Writing to Register Examples
        2. 9.5.3.2 Reading from Register Example
      4. 9.5.4 Streaming Examples
        1. 9.5.4.1 Normal Streaming Example
        2. 9.5.4.2 Controlled Streaming Example
    6. 9.6 Register Maps
      1. 9.6.1 Power and Reset Registers
      2. 9.6.2 ADC Registers
      3. 9.6.3 Channel Configuration Registers  
      4. 9.6.4 Calibration Registers
      5. 9.6.5 Sensor Diagnostic Registers
      6. 9.6.6 SPI Registers
      7. 9.6.7 GPIO Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Connecting the Supplies
        1. 10.1.1.1 VA and VIO
        2. 10.1.1.2 VREF
      2. 10.1.2 Quick Start
      3. 10.1.3 ADC_DOUT Calculation
    2. 10.2 Typical Applications
      1. 10.2.1 Typical Sensor Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 3-Wire RTD
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Thermocouple and IC Analog Temperature
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Device Nomenclature
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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8 Specifications

8.1 Absolute Maximum Ratings

See (2)(1)(4)(5).
MIN MAX UNIT
Analog Supply Voltage, VA –0.3 6.0 V
Digital I/O Supply Voltage, VIO –0.3 6.0
Reference Voltage, VREF –0.3 VA+0.3
Voltage on Any Analog Input Pin to GND(3) –0.3 VA+0.3
Voltage on Any Digital Input PIN to GND(3) –0.3 VIO+0.3
Voltage on SDO(3) –0.3 VIO+0.3
Input Current at Any Pin(3) 5 mA
Output Current Source or Sink by SDO 5
Total Package Input and Output Current 20
Junction Temperature (TJMAX) 150 °C
Storage Temperature (Tstg) –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are measured with respect to GND, unless otherwise specified
(3) When the input voltage (VIN) exceeds the power supply (VIN < GND or VIN > VA), the current at that pin must be limited to 5mA and VIN has to be within the Absolute Maximum Rating for that pin. The 20 mA package input current rating limits the number of pins that can safely exceed the power supplies with current flow to four pins.
(4) For soldering specifications see product folder at http://www.ti.com and http://www.ti.com/lit/SNOA549
(5) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications.

8.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1250
Machine models (MM) ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

MIN MAX UNIT
Analog Supply Voltage, VA 2.85 5.5 V
Digital I/O Supply Voltage, VIO 2.7 5.5
Full Scale Input Range, VIN ±VREF / PGA
Reference Voltage, VREF 0.5 VA
Temperature Range for Electrical Characteristics –40 125 °C
Operating Temperature Range –40 125
Junction to Ambient Thermal Resistance (RθJA)(1) 41 °C/W
(1) The maximum power dissipation is a function of TJ(MAX) AND RθJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA) / RθJA.

8.4 Thermal Information

THERMAL METRIC(1) LMP900xx UNIT
HTSSOP (28 PINS)
RθJA Junction-to-ambient thermal resistance 41 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

Unless otherwise noted, the key for the condition is (VA = VIO = VREF) / ODR (SPS) / buffer / calibration / gain . The typical values apply for TA = +25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
n Resolution 16 Bits
ENOB / NFR Effective Number of Bits and Noise Free Resolution 3V / all / ON / OFF / all. Shorted input.  See Table 1 Bits
5V / all / ON / OFF / all. Shorted input.  See Table 3 Bits
ODR Output Data Rates 1.6675  See Table 1 214.6 SPS
Gain FGA × PGA 1  See Table 3 128
INL Integral Non-Linearity(1) 3V / 214.65 / ON / ON / 1 -1 ± 0.5 +1 LSB
3V & 5V / 214.65 / ON / ON / 16 ± 1 LSB
Total Noise 3V / all / ON / ON / all. Shorted input.  See Table 2 µV
5V / all / ON / OFF / all. Shorted input.  See Table 4 µV
OE Offset Error 3V & 5V / all / ON or OFF / ON / all Below Noise Floor (rms) µV
3V / 214.65 / ON / ON / 1 1.22 9.52 µV
3V / 214.65 / ON / ON / 128 0.00838 0.70 µV
5V / 214.65 / ON / ON / 1 1.79 8.25 µV
5V / 214.65 / ON / ON / 128 0.0112 0.63 µV
Offset Drift Over Temp(1) 3V & 5V / 214.65 / ON or OFF/OFF/1-8 100 nV/°C
3V & 5V / 214.65 / ON / ON / 1-8 3 nV/°C
3V & 5V / 214.65 / ON / OFF / 16 25 nV/°C
3V & 5V / 214.65 / ON / ON / 16 0.4 nV/°C
3V & 5V / 214.65 / ON / OFF / 128 6 nV/°C
3V & 5V / 214.65 / ON / ON / 128 0.125 nV/°C
Offset Drift over Time(1) 5V / 214.65 / ON / OFF / 1, TA = 150°C 2360 nV/1000 hours
5V / 214.65 / ON / ON / 1, TA = 150°C 100 nV/1000 hours
GE Gain Error(1) 3V & 5V / 214.65 / ON / ON / 1, TMIN ≤ TA ≤ TMAX -80 80 ppm
3V & 5V / 214.65 / ON / ON / 1 7 ppm
3V & 5V / 13.42 / ON / ON / 16 50 ppm
3V & 5V / 13.42 / ON / ON / 64 50 ppm
3V & 5V / 13.42 / ON / ON / 128 100 ppm
Gain Drift over Temp(1) 3V & 5V / 214.65 / ON / ON / all 0.5 ppm/°C
Gain Drift over Time(1) 5V / 214.65 / ON / OFF / 1, TA = 150°C 5.9 ppm/1000 hours
5V / 214.65 / ON / ON / 1, TA = 150°C 1.6 ppm/1000 hours
CONVERTER CHARACTERISTICS
CMRR Input Common Mode Rejection Ratio DC, 3V / 214.65 / ON / ON / 1,
TMIN ≤ TA ≤ TMAX		 70 dB
DC, 3V / 214.65 / ON / ON / 1 117 dB
DC, 5V / 214.65 / OFF / OFF / 1,
TMIN ≤ TA ≤ TMAX		 90 dB
DC, 5V / 214.65 / OFF / OFF / 1 120 dB
50/60 Hz, 5V / 214.65 / OFF / OFF / 1 117 dB
Reference Common Mode Rejection VREF = 2.5V 101 dB
PSRR Power Supply Rejection Ratio DC, 3V / 214.65 / ON / ON / 1 75 115 dB
DC, 5V / 214.65 / ON / ON / 1 112 dB
NMRR Normal Mode Rejection Ratio(1) 47 Hz to 63 Hz, 5V / 13.42 / OFF / OFF / 1
TMIN ≤ TA ≤ TMAX		 95 dB
Cross-talk(1) 3V / 214.65 / OFF / OFF / 1, TMIN ≤ TA ≤ TMAX 95 dB
3V / 214.65 / OFF / OFF / 1 136 dB
5V / 214.65 / OFF / OFF / 1, TMIN ≤ TA ≤ TMAX 95 dB
5V / 214.65 / OFF / OFF / 1 143 dB
POWER SUPPLY CHARACTERISTICS
VA Analog Supply Voltage 2.85 3.0 5.5 V
VIO Digital Supply Voltage 2.7 3.3 5.5 V
IVA Analog Supply Current 3V / 13.42 / OFF / OFF / 1, ext. CLK 400 µA
3V / 13.42 / OFF / OFF / 1, ext. CLK,
TMIN ≤ TA ≤ TMAX		 500 µA
5V / 13.42 / OFF / OFF / 1, ext. CLK 464 µA
5V / 13.42 / OFF / OFF / 1, ext. CLK,
TMIN ≤ TA ≤ TMAX		 555 µA
3V / 13.42 / ON / OFF / 64, ext. CLK 600 µA
3V / 13.42 / ON / OFF / 64, ext. CLK,
TMIN ≤ TA ≤ TMAX		 700 µA
5V / 13.42 / ON / OFF / 64, ext. CLK 690 µA
5V / 13.42 / ON / OFF / 64, ext. CLK,
TMIN ≤ TA ≤ TMAX		 800 µA
3V / 214.65 / ON / OFF / 64, int. CLK 1547 µA
3V / 214.65 / ON / OFF / 64, int. CLK,
TMIN ≤ TA ≤ TMAX		 1700 µA
5V / 214.65 / ON / OFF / 64, int. CLK 1760 µA
5V / 214.65 / ON / OFF / 64, int. CLK,
TMIN ≤ TA ≤ TMAX		 2000 µA
3V / 214.65 / OFF / OFF / 1, int. CLK 826 µA
3V / 214.65 / OFF / OFF / 1, int. CLK,
TMIN ≤ TA ≤ TMAX		 1000 µA
5V / 214.65 / OFF / OFF / 1, int. CLK 941 µA
5V / 214.65 / OFF / OFF / 1, int. CLK,
TMIN ≤ TA ≤ TMAX		 1100 µA
Standby, 3V , int. CLK 3 10 µA
Standby, 3V , ext. CLK 257 µA
Standby, 5V, int. CLK 5 15 µA
Standby, 3V, ext. CLK 300 µA
Power-down, 3V, int/ext CLK 2.6 µA
Power-down, 3V, int/ext CLK, TMIN ≤ TA ≤ TMAX 5 µA
Power-down, 5V, int/ext CLK 4.6 µA
Power-down, 5V, int/ext CLK, TMIN ≤ TA ≤ TMAX 9 µA
REFERENCE INPUT
VREFP Positive Reference VREFN + 0.5 VA V
VREFN Negative Reference GND VREFP - 0.5 V
VREF Differential Reference VREF = VREFP - VREFN 0.5 VA V
ZREF Reference Impedance 3V / 13.42 / OFF / OFF / 1 10 MΩ
IREF Reference Input 3V / 13.42 / ON or OFF /ON or OFF/all ±2 µA
CREFP Capacitance of the Positive Reference gain = 1(1) 6 pF
CREFN Capacitance of the Negative Reference gain = 1(1) 6 pF
ILREF Reference Leakage Current Power-down 1 nA
ANALOG INPUT
VINP Positive Input Gain = 1-8, buffer ON GND + 0.1 VA - 0.1 V
Gain = 16 - 128, buffer ON GND + 0.4 VA - 1.5 V
Gain = 1-8, buffer OFF GND VA V
VINN Negative Input Gain = 1-8, buffer ON GND + 0.1 VA - 0.1 V
Gain = 16 - 128, buffer ON GND + 0.4 VA - 1.5 V
Gain = 1-8, buffer OFF GND VA V
VIN Differential Input VIN = VINP - VINN ±VREF / PGA
ZIN Differential Input Impedance ODR = 13.42 SPS 15.4 MΩ
CINP Capacitance of the Positive Input 5V / 214.65 / OFF / OFF / 1 4 pF
CINN Capacitance of the Negative Input 5V / 214.65 / OFF / OFF / 1 4 pF
IIN Input Leakage Current 3V & 5V / 13.42 / ON / OFF / 1-8 500 pA
3V & 5V / 13.42 / ON / OFF / 16 - 128 100 pA
DIGITAL INPUT CHARACTERISTICS at VA = VIO = VREF = 3.0 V
VIH Logical "1" Input Voltage 0.7 x VIO V
VIL Logical "0" Input Voltage 0.3 x VIO V
IIL Digital Input Leakage Current -10 +10 µA
VHYST Digital Input Hysteresis 0.1 x VIO V
DIGITAL OUTPUT CHARACTERISTICS at VA = VIO = VREF = 3.0 V
VOH Logical "1" Output Voltage Source 300 µA 2.6 V
VOL Logical "0" Output Voltage Sink 300 µA 0.4 V
IOZH, IOZL TRI-STATE Leakage Current -10 10 µA
COUT TRI-STATE Capacitance See(1) 5 pF
EXCITATION CURRENT SOURCES CHARACTERISTICS (LMP90080/LMP90078 ONLY)
IB1, IB2 Excitation Current Source Output 0, 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000 µA
IB1/IB2 Tolerance VA = VREF = 3V 2.5%
VA = VREF = 3V, TMIN ≤ TA ≤ TMAX -7% 7%
VA = VREF = 5V 0.2%
VA = VREF = 5V, TMIN ≤ TA ≤ TMAX -3.5% 3.5%
IB1/IB2 Output Compliance Range VA = 3.0V & 5.0V, IB1/IB2 = 100 µA to 1000 µA VA - 0.8 V
IB1/IB2 Regulation VA = 5.0V, IB1/IB2 = 100 µA to 1000 µA 0.07 %/V
IBTC IB1/IB2 Drift VA = 3.0V 95 ppm/°C
VA = 5.0V 60 ppm/°C
IBMT IB1/IB2 Matching 3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 100 µA		 0.34%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 100 µA, TMIN ≤ TA ≤ TMAX		 1.53%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 200 µA		 0.22%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 200 µA, TMIN ≤ TA ≤ TMAX		 1%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 300 µA		 0.2%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 300 µA, TMIN ≤ TA ≤ TMAX		 0.85%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 400 µA		 0.15%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 400 µA, TMIN ≤ TA ≤ TMAX		 0.8%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 500 µA		 0.14%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 500 µA, TMIN ≤ TA ≤ TMAX		 0.7%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 600 µA		 0.13%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 600 µA, TMIN ≤ TA ≤ TMAX		 0.7%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 700 µA		 0.075%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 700 µA, TMIN ≤ TA ≤ TMAX		 0.65%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 800 µA		 0.085%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 800 µA, TMIN ≤ TA ≤ TMAX		 0.6%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 900 µA		 0.11%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 900 µA,TMIN ≤ TA ≤ TMAX		 0.55%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 1000 µA		 0.11%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 1000 µA, TMIN ≤ TA ≤ TMAX		 0.45%
IBMTC IB1/IB2 Matching Drfit VA = 3.0V & 5.0V, IB1/IB2 = 100 µA to 1000 µA 2 ppm/°C
INTERNAL/EXTERNAL CLK
CLKIN Internal Clock Frequency 893 kHz
CLKEXT External Clock Frequency See(1) 1.8 3.5717 7.2 MHz
External Crystal Frequency Input Low Voltage 0 V
Input High Voltage 1 V
Frequency 1.8 3.5717 7.2 MHz
Start-up time 7 ms
SCLK Serial Clock 10 MHz
(1) This parameter is specified by design and/or characterization and is not tested in production.

8.6 Timing Requirements

Unless otherwise noted, specified limits apply for VA = VIO = 3 V. The typical values apply for TA = 25°C.
MIN NOM MAX UNIT
fSCLK See Figure 1. 10 MHz
tCH SCLK High time 0.4 / fSCLK ns
tCL SCLK Low time 0.4 / fSCLK ns

8.7 Timing Requirements - CSB Timing

MIN NOM MAX UNIT
tCSSU CSB Setup time prior to an SCLK rising edge See Figure 2. 5 ns
tCSH CSB Hold time after the last rising edge of SCLK See Figure 3. 6 ns

8.8 Timing Requirements - SCLK and SDI Timing

MIN NOM MAX UNIT
tCLKR SCLK Rise time See Figure 4. 1.15 ns
tCLKF SCLK Fall time 1.15 ns
tDISU SDI Setup time prior to an SCLK rising edge See Figure 5. 5 ns
tDIH SDI Hold time after an SCLK rising edge 6 ns

8.9 Timing Requirements - SDO Timing With DOD1

MIN NOM MAX UNIT
tDOA SDO Access time after an SCLK falling edge See Figure 6. 35 ns
tDOH SDO Hold time after an SCLK falling edge 5 ns
tDOD1 SDO Disable time after the rising edge of CSB See Figure 7. 27 ns

8.10 Timing Requirements - SDO Timing with DOD2

MIN NOM MAX UNIT
tDOD2 SDO Disable time after either edge of SCLK See Figure 8 and Figure 9. 27 ns

8.11 Timing Requirements - SDO and DRDYB Timing

MIN NOM MAX UNIT
tDOE SDO Enable time from the falling edge of the 8th SCLK See Figure 10. 35 ns
tDOR SDO Rise time(1) See Figure 11. 7 ns
tDOF SDO Fall time(1) 7 ns
tDRDYB Data Ready Bar pulse at every
1/ODR second		 ODR ≤ 13.42 SPS 64 µs
13.42 < ODR ≤ 214.65 SPS 4 µs
(1) This parameter is specified by design and/or characterization and is not tested in production.
LMP90077 LMP90078 LMP90079 LMP90080 30169701.gif Figure 1. Timing Diagram
LMP90077 LMP90078 LMP90079 LMP90080 30169702.gif Figure 2. CBS Setup Time
LMP90077 LMP90078 LMP90079 LMP90080 30169703.gif Figure 3. CBS Hold Time
LMP90077 LMP90078 LMP90079 LMP90080 30169704.gif Figure 4. SCLK Rise and Fall Time
LMP90077 LMP90078 LMP90079 LMP90080 30169705.gif Figure 5. SCLK Setup and Hold Time
LMP90077 LMP90078 LMP90079 LMP90080 30169706.gif Figure 6. SDO Enable Time
LMP90077 LMP90078 LMP90079 LMP90080 30169707.gif Figure 7. SDO Rise and Fall Time
LMP90077 LMP90078 LMP90079 LMP90080 30169708.gif Figure 8. SDO Disable Time
LMP90077 LMP90078 LMP90079 LMP90080 30169709.gif Figure 9. SDO Rise and Fall Time
LMP90077 LMP90078 LMP90079 LMP90080 30169710.gif Figure 10. SDO Enable Time
LMP90077 LMP90078 LMP90079 LMP90080 30169711.gif Figure 11. SDO Rise and Fall Time

Table 1. ENOB (Noise Free Resolution) vs Sampling Rate and Gain At VA = VIO = VREF = 3V

ODR (SPS) GAIN
1 2 4 8 16 32 64 128
1.6775 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5)
3.355 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (14.5)
6.71 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (16) 16 (16) 16 (15) 16 (14.5)
13.42 16 (16) 16 (16) 16 (15.5) 16 (15) 16 (16) 16 (15.5) 16 (15) 16 (14)
26.83125 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (15)
53.6625 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15) 16 (14.5)
107.325 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (16) 16 (15.5) 16 (14.5) 16 (14)
214.65 16 (16) 16 (16) 16 (15.5) 16 (15) 16 (16) 16 (15) 16 (14.5) 16 (13.5)

Table 2. RMS Noise (mV) vs Sampling Rate and Gain At VA = VIO = VREF = 3V

ODR (SPS) GAIN OF THE ADC
1 2 4 8 16 32 64 128
1.6775 3.08 1.90 1.53 1.27 0.23 0.21 0.15 0.14
3.355 4.56 2.70 2.21 1.67 0.34 0.27 0.24 0.26
6.71 6.15 4.10 3.16 2.39 0.51 0.40 0.37 0.35
13.42 8.60 5.85 4.29 3.64 0.67 0.54 0.51 0.49
26.83125 3.35 2.24 1.65 1.33 0.33 0.27 0.26 0.25
53.6625 4.81 3.11 2.37 1.90 0.44 0.39 0.37 0.36
107.325 6.74 4.51 3.38 2.66 0.63 0.54 0.52 0.49
214.65 9.52 6.37 4.72 3.79 0.90 0.79 0.72 0.70

Table 3. ENOB (Noise Free Resolution) vs Sampling Rate and Gain At VA = VIO = VREF = 5V

SPS GAIN OF THE ADC
1 2 4 8 16 32 64 128
1.6775 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16)
3.355 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5)
6.71 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15)
13.42 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (15)
26.83125 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5)
53.6625 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15)
107.325 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (14.5)
214.65 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15) 16 (14)

Table 4. RMS Noise (mV) vs. Sampling Rate and Gain At VA = VIO = VREF = 5V

SPS GAIN OF THE ADC
1 2 4 8 16 32 64 128
1.6775 2.68 1.65 1.24 1.00 0.22 0.19 0.17 0.16
3.355 3.86 2.36 1.78 1.47 0.34 0.27 0.22 0.22
6.71 5.23 3.49 2.47 2.09 0.44 0.34 0.30 0.32
13.42 7.94 5.01 3.74 2.94 0.61 0.50 0.45 0.43
26.83125 2.90 1.86 1.34 1.08 0.29 0.24 0.23 0.23
53.6625 4.11 2.60 1.90 1.50 0.39 0.35 0.32 0.31
107.325 5.74 3.72 2.72 2.11 0.56 0.48 0.46 0.44
214.65 8.25 5.31 3.82 2.97 0.79 0.68 0.64 0.63

8.12 Typical Characteristics

Unless otherwise noted, specified limits apply for VA = VIO = VREF = 3.0 V. The maximum and minimum values apply for TA = TMIN to TMAX; the typical values apply for TA = 25°C.
LMP90077 LMP90078 LMP90079 LMP90080 30169715.gif Figure 12. Noise Measurement Without Calibration
at Gain = 1
LMP90077 LMP90078 LMP90079 LMP90080 30169721.gif Figure 14. Histogram Without Calibration
at Gain = 1
LMP90077 LMP90078 LMP90079 LMP90080 30169717.gif Figure 16. Noise Measurement Without Calibration
at Gain = 8
LMP90077 LMP90078 LMP90079 LMP90080 30169723.gif Figure 18. Histogram Without Calibration
at Gain = 8
LMP90077 LMP90078 LMP90079 LMP90080 30169719.gif Figure 20. Noise Measurement Without Calibration
at Gain = 128
LMP90077 LMP90078 LMP90079 LMP90080 30169725.gif Figure 22. Histogram Without Calibration
at Gain = 128
LMP90077 LMP90078 LMP90079 LMP90080 30169741.gif Figure 24. Noise vs. Gain Without Calibration
at ODR = 13.42 SPS
LMP90077 LMP90078 LMP90079 LMP90080 30169749.gif Figure 26. Noise vs. Gain Without Calibration
at ODR = 214.65 SPS
LMP90077 LMP90078 LMP90079 LMP90080 30169761.gif Figure 28. Offset Error vs. Temperature Without Calibration
at Gain = 1
LMP90077 LMP90078 LMP90079 LMP90080 30169762.gif Figure 30. Offset Error vs. Temperature Without Calibration
at Gain = 8
LMP90077 LMP90078 LMP90079 LMP90080 30169767.gif Figure 32. Gain Error vs. Temperature Without Calibration
at Gain = 1
LMP90077 LMP90078 LMP90079 LMP90080 30169768.gif Figure 34. Gain Error vs. Temperature Without Calibration
at Gain = 8
LMP90077 LMP90078 LMP90079 LMP90080 30169751.gif Figure 36. Digital Filter Frequency Response
LMP90077 LMP90078 LMP90079 LMP90080 30169727.gif Figure 38. INL at Gain = 1
LMP90077 LMP90078 LMP90079 LMP90080 30169716.gif Figure 13. Noise Measurement With Calibration
at Gain = 1
LMP90077 LMP90078 LMP90079 LMP90080 30169722.gif Figure 15. Histogram With Calibration
at Gain = 1
LMP90077 LMP90078 LMP90079 LMP90080 30169718.gif Figure 17. Noise Measurement With Calibration
at Gain = 8
LMP90077 LMP90078 LMP90079 LMP90080 30169724.gif Figure 19. Histogram With Calibration
at Gain = 8
LMP90077 LMP90078 LMP90079 LMP90080 30169720.gif Figure 21. Noise Measurement With Calibration
at Gain = 128
LMP90077 LMP90078 LMP90079 LMP90080 30169726.gif Figure 23. Histogram With Calibration
at Gain = 128
LMP90077 LMP90078 LMP90079 LMP90080 30169748.gif Figure 25. Noise vs. Gain With Calibration
at ODR = 13.42 SPS
LMP90077 LMP90078 LMP90079 LMP90080 30169750.gif Figure 27. Noise vs. Gain With Calibration
at ODR = 214.65 SPS
LMP90077 LMP90078 LMP90079 LMP90080 30169764.gif Figure 29. Offset Error vs. Temperature With Calibration
at Gain = 1
LMP90077 LMP90078 LMP90079 LMP90080 30169765.gif Figure 31. Offset Error vs. Temperature With Calibration
at Gain = 8
LMP90077 LMP90078 LMP90079 LMP90080 30169770.gif Figure 33. Gain Error vs. Temperature With Calibration
at Gain = 1
LMP90077 LMP90078 LMP90079 LMP90080 30169771.gif Figure 35. Gain Error vs. Temperature With Calibration
at Gain = 8
LMP90077 LMP90078 LMP90079 LMP90080 30169753.gif Figure 37. Digital Filter Frequency Response