SNVSAG2B
November 2015 – December 2024
LMR14050-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics
5.7
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Fixed Frequency Peak Current Mode Control
6.3.2
Slope Compensation
6.3.3
Sleep-mode
6.3.4
Low Dropout Operation and Bootstrap Voltage (BOOT)
6.3.5
Adjustable Output Voltage
6.3.6
Enable and Adjustable Undervoltage Lockout
6.3.7
External Soft-start
6.3.8
Switching Frequency and Synchronization (RT/SYNC)
6.3.9
Power Good (PGOOD)
6.3.10
Overcurrent and Short-Circuit Protection
6.3.11
Overvoltage Protection
6.3.12
Thermal Shutdown
6.4
Device Functional Modes
6.4.1
Shutdown Mode
6.4.2
Active Mode
6.4.3
CCM Mode
6.4.4
Light Load Operation
7
Application and Implementation
7.1
Application Information
7.2
Typical Application
7.2.1
Design Requirements
7.2.2
Detailed Design Procedure
7.2.2.1
Output Voltage Set-Point
7.2.2.2
Switching Frequency
7.2.2.3
Output Inductor Selection
7.2.2.4
Output Capacitor Selection
7.2.2.5
Schottky Diode Selection
7.2.2.6
Input Capacitor Selection
7.2.2.7
Bootstrap Capacitor Selection
7.2.2.8
Soft-start Capacitor Selection
7.2.3
Application Curves
7.3
Power Supply Recommendations
7.4
Layout
7.4.1
Layout Guidelines
7.4.2
Layout Example
8
Device and Documentation Support
8.1
Device Support
8.1.1
Third-Party Products Disclaimer
8.2
Documentation Support
8.2.1
Related Documentation
8.2.2
Related Products
8.3
Receiving Notification of Documentation Updates
8.4
Support Resources
8.5
Trademarks
8.6
Electrostatic Discharge Caution
8.7
Glossary
9
Revision History
10
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DDA|8
MPDS092F
DPR|10
MPSS046B
サーマルパッド・メカニカル・データ
DDA|8
PPTD178C
発注情報
snvsag2b_oa
snvsag2b_pm
5.2
ESD Ratings
VALUE
UNIT
V
(ESD)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1)
±2000
V
Charged-device model (CDM), per AEC Q100-011
±750
(1)
AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.