Table 2. Design Example Parameters

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMR23610-Q1 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Output Voltage Set-Point

The output voltage of LMR23610-Q1 is externally adjustable using a resistor divider network. The divider network is comprised of top feedback resistor R_FBT and bottom feedback resistor R_FBB. Equation 10 is used to determine the output voltage:

Equation 10.

Choose the value of R_FBB to be 22.1 kΩ. With the desired output voltage set to 5 V and the V_REF = 1.0 V, the R_FBB value can then be calculated using Equation 10. The formula yields to a value 88.7 kΩ.

8.2.2.3 Switching Frequency

The default switching frequency of the LMR23610-Q1 is 400 kHz. For other switching frequency, the device must be synchronized to an external clock, please refer to Enable/Sync for more details.

8.2.2.4 Inductor Selection

The most critical parameters for the inductor are the inductance, saturation current and the rated current. The inductance is based on the desired peak-to-peak ripple current Δi_L. Since the ripple current increases with the input voltage, the maximum input voltage is always used to calculate the minimum inductance L_MIN. Use Equation 12 to calculate the minimum value of the output inductor. K_IND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current of the device. A reasonable value of K_IND should be 30% to 50%. During an instantaneous short or over current operation event, the RMS and peak inductor current can be high. The inductor current rating should be higher than the current limit of the device.

Equation 11.

Equation 12.

In general, it is preferable to choose lower inductance in switching power supplies, because it usually corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But too low of an inductance can generate too large of an inductor current ripple such that over current protection at the full load could be falsely triggered. It also generates more conduction loss and inductor core loss. Larger inductor current ripple also implies larger output voltage ripple with same output capacitors. With peak current mode control, it is not recommended to have too small of an inductor current ripple. A larger peak current ripple improves the comparator signal to noise ratio.

For this design example, choose K_IND = 0.5, the minimum inductor value is calculated to be 20.5 µH. Choose the nearest standard 22 μH ferrite inductor with a capability of 2 A RMS current and 2.5 A saturation current.

8.2.2.5 Output Capacitor Selection

The output capacitor(s), C_OUT, should be chosen with care since it directly affects the steady state output voltage ripple, loop stability and the voltage over/undershoot during load current transients.

The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going through the Equivalent Series Resistance (ESR) of the output capacitors:

Equation 13.

The other is caused by the inductor current ripple charging and discharging the output capacitors:

Equation 14.

The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the sum of two peaks.

Output capacitance is usually limited by transient performance specifications if the system requires tight voltage regulation with presence of large current steps and fast slew rate. When a fast large load increase happens, output capacitors provide the required charge before the inductor current can slew up to the appropriate level. The regulator’s control loop usually needs six or more clock cycles to respond to the output voltage droop. The output capacitance must be large enough to supply the current difference for six clock cycles to maintain the output voltage within the specified range. Equation 15 shows the minimum output capacitance needed for specified output undershoot. When a sudden large load decrease happens, the output capacitors absorb energy stored in the inductor. which results in an output voltage overshoot. Equation 16 calculates the minimum capacitance required to keep the voltage overshoot within a specified range.

Equation 15.

Equation 16.

where

• K_IND = Ripple ratio of the inductor ripple current (Δi_L / I_OUT)
• I_OL = Low level output current during load transient
• I_OH = High level output current during load transient
• V_US = Target output voltage undershoot
• V_OS = Target output voltage overshoot

For this design example, the target output ripple is 50 mV. Presuppose ΔV_{OUT_ESR} = ΔV_{OUT_C} = 50 mV, and chose K_IND = 0.5. Equation 13 yields ESR no larger than 100 mΩ and Equation 14 yields C_OUT no smaller than 3.1 μF. For the target over/undershoot range of this design, V_US = V_OS = 5% × V_OUT = 250 mV. The C_OUT can be calculated to be no smaller than 54 μF and 8.5 μF by Equation 15 and Equation 16 respectively. Consider of derating, one 82 μF, 16 V ceramic capacitor with 5 mΩ ESR is used.

8.2.2.6 Feed-Forward Capacitor

The LMR23610-Q1 is internally compensated. Depending on the V_OUT and frequency f_SW, if the output capacitor C_OUT is dominated by low ESR (ceramic types) capacitors, it could result in low phase margin. To improve the phase boost an external feedforward capacitor C_FF can be added in parallel with R_FBT. C_FF is chosen such that phase margin is boosted at the crossover frequency without C_FF. A simple estimation for the crossover frequency (f_X) without C_FF is shown in Equation 17, assuming C_OUT has very small ESR, and C_OUT value is after derating.

Equation 17.

The following equation for C_FF was tested:

Equation 18.

For designs with higher ESR, C_FF is not needed when C_OUT has very high ESR and C_FF calculated from Equation 18 should be reduced with medium ESR. Table 1 can be used as a quick starting point.

For the application in this design example, a 75 pF, 50 V, COG capacitor is selected.

8.2.2.7 Input Capacitor Selection

The LMR23610-Q1 device requires high frequency input decoupling capacitor(s) and a bulk input capacitor, depending on the application. The typical recommended value for the high frequency decoupling capacitor is 4.7 μF to 10 μF. A high-quality ceramic capacitor type X5R or X7R with sufficiency voltage rating is recommended. To compensate the derating of ceramic capacitors, a voltage rating of twice the maximum input voltage is recommended. Additionally, some bulk capacitance can be required, especially if the LMR23610-Q1 circuit is not located within approximately 5 cm from the input voltage source. This capacitor is used to provide damping to the voltage spike due to the lead inductance of the cable or the trace. For this design, two 4.7 μF, 50 V, X7R ceramic capacitors are used. A 0.1 μF for high-frequency filtering and place it as close as possible to the device pins.

8.2.2.8 Bootstrap Capacitor Selection

Every LMR23610-Q1 design requires a bootstrap capacitor (C_BOOT). The recommended capacitor is 0.1 μF and rated 16 V or higher. The bootstrap capacitor is located between the SW pin and the BOOT pin. The bootstrap capacitor must be a high-quality ceramic type with an X7R or X5R grade dielectric for temperature stability.

8.2.2.9 VCC Capacitor Selection

The VCC pin is the output of an internal LDO for LMR23610-Q1. To insure stability of the device, place a minimum of 2.2 μF, 16 V, X7R capacitor from this pin to ground.

8.2.2.10 Under Voltage Lockout Set-Point

The system undervoltage lockout (UVLO) is adjusted using the external voltage divider network of R_ENT and R_ENB.  The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. The following equation can be used to determine the V_IN UVLO level.

Equation 19.

The EN rising threshold (V_ENH) for LMR23610-Q1 is set to be 1.55 V (typ). Choose the value of R_ENB to be 287 kΩ to minimize input current from the supply. If the desired V_IN UVLO level is at 6.0 V, then the value of R_ENT can be calculated using the equation below:

Equation 20.

The above equation yields a value of 820 kΩ. The resulting falling UVLO threshold, equals 4.4 V, can be calculated by below equation, where EN hysteresis (V_{EN_HYS}) is 0.4 V (typ).

Equation 21.