9.1 Layout Considerations

The LMR24210 regulation, overvoltage, and current limit comparators are very fast and may respond to short duration noise pulses. Layout is therefore critical for optimum performance. It must be as neat and compact as possible, and all external components must be as close to their associated pins of the LMR24210 as possible. Refer to the Functional Block Diagram, the loop formed by C_IN, the main and synchronous MOSFET internal to the LMR24210, and the PGND pin must be as small as possible. The connection from the PGND pin to C_IN must be as short and direct as possible. Add vias to connect the ground of C_IN to a ground plane, located as close as possible to the capacitor. The bootstrap capacitor C_BST should be connected as close to the SW and BST pins as possible, and the connecting traces should be thick. The feedback resistors and capacitor R_FB1, R_FB2, and C_FB must be close to the FB pin. A long trace running from V_OUT to R_FB1 is generally acceptable since this is a low impedance node. Ground R_FB2 directly to the AGND pin. Connect the output capacitor C_OUT to the load and tied directly to the ground plane. Connect the inductor L close to the SW pin with as short a trace as possible to reduce the potential for EMI (electromagnetic interference) generation. If it is expected that the internal dissipation of the LMR24210 produces excessive junction temperature during normal operation, making good use of the PC board’s ground plane can help considerably to dissipate heat. Additionally the use of thick traces, where possible, can help conduct heat away from the LMR24210. Judicious positioning of the PC board within the end product, along with the use of any available air flow (forced or natural convection) can help reduce the junction temperature.