JAJSFN3C
June 2018 – October 2020
LMR33630-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Characteristics
6.7
System Characteristics
6.8
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Power-Good Flag Output
7.3.2
Enable and Start-up
7.3.3
Current Limit and Short Circuit
7.3.4
Undervoltage Lockout and Thermal Shutdown
7.4
Device Functional Modes
7.4.1
Auto Mode
7.4.2
Dropout
7.4.3
Minimum Switch On-Time
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Custom Design With WEBENCH® Tools
8.2.2.2
Choosing the Switching Frequency
8.2.2.3
Setting the Output Voltage
8.2.2.4
Inductor Selection
8.2.2.5
Output Capacitor Selection
8.2.2.6
Input Capacitor Selection
8.2.2.7
CBOOT
8.2.2.8
VCC
8.2.2.9
CFF Selection
8.2.2.10
External UVLO
8.2.2.11
Maximum Ambient Temperature
8.2.3
Application Curves
8.3
What to Do and What Not to Do
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.1.1
Ground and Thermal Considerations
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Development Support
11.1.1.1
Custom Design With WEBENCH® Tools
11.2
Documentation Support
11.2.1
Related Documentation
11.3
サポート・リソース
11.4
ドキュメントの更新通知を受け取る方法
11.5
Trademarks
11.6
静電気放電に関する注意事項
11.7
用語集
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
RNX|12
サーマルパッド・メカニカル・データ
RNX|12
QFND597B
発注情報
jajsfn3c_oa
jajsfn3c_pm
7.2
Functional Block Diagram