JAJSM65A march   2023  – may 2023 LMR36501 , LMR36502

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD (Commercial) Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable, Shutdown, and Start-up
      2. 8.3.2  Adjustable Switching Frequency (with RT)
      3. 8.3.3  Power-Good Output Operation
      4. 8.3.4  Internal LDO, VCC UVLO, and VOUT/FB Input
      5. 8.3.5  Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      6. 8.3.6  Output Voltage Selection
      7. 8.3.7  Soft Start and Recovery from Dropout
        1. 8.3.7.1 Soft Start
        2. 8.3.7.2 Recovery from Dropout
      8. 8.3.8  Current Limit and Short Circuit
      9. 8.3.9  Thermal Shutdown
      10. 8.3.10 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 CCM Mode
        2. 8.4.3.2 AUTO Mode - Light Load Operation
          1. 8.4.3.2.1 Diode Emulation
          2. 8.4.3.2.2 Frequency Reduction
        3. 8.4.3.3 FPWM Mode - Light Load Operation
        4. 8.4.3.4 Minimum On-time Operation
        5. 8.4.3.5 Dropout
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Choosing the Switching Frequency
        2. 9.2.2.2  Setting the Output Voltage
          1. 9.2.2.2.1 VOUT / FB for Adjustable Output
        3. 9.2.2.3  Inductor Selection
        4. 9.2.2.4  Output Capacitor Selection
        5. 9.2.2.5  Input Capacitor Selection
        6. 9.2.2.6  CBOOT
        7. 9.2.2.7  VCC
        8. 9.2.2.8  CFF Selection
        9. 9.2.2.9  External UVLO
        10. 9.2.2.10 Maximum Ambient Temperature
      3. 9.2.3 Application Curves
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
        1. 9.5.1.1 Ground and Thermal Considerations
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.1 Enable, Shutdown, and Start-up

The voltage at the EN/UVLO pin controls the start-up voltage and shutdown voltage of the LMR3650x. There are three distinct modes set by the EN/UVLO pin; shut-down, standby and active. As long as the EN/UVLO pin voltage is less than VEN-WAKE the device is shutdown mode. During shutdown mode, the input current drawn by the device typically is 0.5 µA (VIN = 13.5 V). The internal LDO regulator is not operational. When the voltage at the EN/UVLO pin is greater than the VEN-WAKE but less than VEN-VOUT the device enters the standby mode. In standby mode, the internal LDO is enabled. As the EN/UVLO pin voltage increases above VEN-VOUT, the device enters active mode starting the feedback resistor detection. After feedback detect is completed, soft-start functionality is released to slowly increases the output voltage and switching starts. To stop switching and enter standby mode the EN/UVLO pin must fall below (VEN-VOUT – VEN-HYST). Any further decrease in the EN/UVLO pin voltage below VEN-WAKE the device is in shutdown. The various EN/UVLO threshold parameters and their values are listed in Section 7.5. See Section 8.3.6 for information about feedback resistor detection. Figure 8-1 shows the precision enable behavior.

GUID-20220210-SS0I-VFT6-Q8M9-F2HF8GKGZXL2-low.svg Figure 8-1 Precision Enable Behavior

Remote precision undervoltage lockout can be implemented with this functionality as shown in Figure 8-2. See Section 9.2.2.9 for component selection.

GUID-F39ED1E0-32C0-42AE-9D4F-48878FDAC48A-low.gif Figure 8-2 VIN Undervoltage Lockout
Using the EN/UVLO Pin

The high-voltage compliant EN/UVLO pin can be connected directly to the VIN input pin if remote precision control is not needed. The EN/UVLO pin must not be allowed to float. The various EN threshold parameters are listed in the Section 7.5. Figure 8-1 shows the precision enable behavior. After EN/UVLO goes above VEN-VOUT with a delay of about 1 ms, the output voltage begins to rise with a soft-start and reaches close to the final value in about 2.58 ms (tss). After a delay of about 2 ms (tPGOOD_ACT), the PGOOD flag goes high. During startup, the device is not allowed to enter FPWM mode until the soft-start time has elapsed. Check Section 9.2.2.9 for component selection.