JAJSNA5B February   2023  – January 2024 LMR38010-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency Peak Current Mode Control
      2. 7.3.2  Adjustable Output Voltage
      3. 7.3.3  Enable
      4. 7.3.4  Switching Frequency and Synchronization (RT/SYNC)
      5. 7.3.5  Power-Good Flag Output
      6. 7.3.6  Minimum On Time, Minimum Off Time, and Frequency Foldback
      7. 7.3.7  Bootstrap Voltage
      8. 7.3.8  Overcurrent and Short Circuit Protection
      9. 7.3.9  Soft Start
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto Mode
      2. 7.4.2 Forced PWM Operation
      3. 7.4.3 Dropout
      4. 7.4.4 Minimum Switch On Time
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Choosing the Switching Frequency
        3. 8.2.2.3 FB for Adjustable Output
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Output Capacitor Selection
        6. 8.2.2.6 Input Capacitor Selection
        7. 8.2.2.7 CBOOT
        8. 8.2.2.8 External UVLO
        9. 8.2.2.9 Maximum Ambient Temperature
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground and Thermal Considerations
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Limits apply over operating junction temperature (TJ ) range of –40°C to +150°C, unless otherwise stated. Minimum and Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE AND CURRENT
VIN_OPERATE Input operating voltage Needed to start up 4.2 V
Once operating 3.8 V
IQ(Non-SW) Non-switching quiescent current VEN = 3.3 V (PFM variant only) 40 µA
ISD Shutdown quiescent current; measured at VIN pin VEN = 0 V 3 10 µA
ENABLE
VEN-H Enable input high level VEN rising 1.1 1.25 1.4 V
VEN-L Enable input low level VEN falling 0.95 1.10 1.22 V
ILKG-EN Enable input leakage current VEN = 3.3V 5.0 nA
VOLTAGE REFERENCE (FB PIN)
VREF Feedback reference voltage Vin=4.2V to 80V, TJ=25°C, FPWM 0.99 1 1.01 V
VREF Feedback reference voltage FPWM 0.985 1 1.015 V
ILKG-FB Feedback leakage current FB = 1.2 V 2.1 nA
CURRENT LIMITS AND HICCUP
IHS-LIMIT High-side current limit(2) 1A Version 1.3 1.6 1.9 A
ILS-LIMIT Low-side current limit(2) 1A Version 0.9 1.2 1.5 A
IL-ZC Zero cross detector threshold PFM variants only 0.01 A
IPEAK-MIN Minimum inductor peak current(2) 1A Version, PFM variants only 0.25 A
IL-NEG Negative current limit(2) 1A Version, FPWM variant only –0.5 A
POWER STAGE
RDS-ON-HS High-side MOSFET ON-resistance 303 mΩ
RDS-ON-LS Low-side MOSFET ON-resistance 133 mΩ
tON-MIN Minimum switch on-time(3) VIN =24 V, Iout = 1 A 80 131 ns
tOFF-MIN Minimum switch off-time 190 300 ns
tON-MAX Maximum switch on-time 5 us
SWITCHING FREQUENCY AND SYNCHRONIZATION
FOSC Switching frequency RT = 64.9 kΩ 320 400 480 kHz
FSPREAD Spread of internal oscillator with Spread
Spectrum Enabled		 -8 8 %
VSYNC_HI SYNC clock high level threshold 2 V
VSYNC_LO SYNC clock low level threshold 0.6 V
tPULSE_H High duration needed to be recognized as a pulse 50 ns
CLOCK Time needed for clock to lock to a valid synchronization signal in sync cycles 230 us
STARTUP AND TRACKING
tSS Internal soft-start time 4 ms
POWER GOOD
VPG-HIGH-UP Power-Good upper threshold - rising % of FB voltage 110% 112% 114%
VPG-LOW-DN Power-Good lower threshold - falling % of FB voltage 90% 92% 94%
VPG-HYS Power-Good hysteresis (rising & falling) % of FB voltage 2.2%
VPG-VALID Minimum input voltage for proper Power-Good function 2 V
RPG Power-Good on-resistance VEN = 0 V 140 Ω
RPG Power-Good on-resistance VEN = 3.3V 92 Ω
tPGDFLT(fall) Glitch filter time constant for PGOOD function 40 us
THERMAL SHUTDOWN
TSD-Rising(4) Thermal shutdown Shutdown threshold 163 ℃
TSD-Falling(4) Thermal shutdown Recovery threshold 150 ℃
(1) MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.
(3) Not production tested. Specified by correlation by design at 1A load
(4) Not production tested. Specified by design