JAJSV98 August   2024 LMR51460-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency Peak Current Mode Control
      2. 7.3.2  Adjustable Output Voltage
      3. 7.3.3  Enable
      4. 7.3.4  Switching Frequency
      5. 7.3.5  Power-Good Flag Output
      6. 7.3.6  Minimum ON-Time, Minimum OFF-Time, and Frequency Foldback
      7. 7.3.7  Bootstrap Voltage
      8. 7.3.8  Overcurrent and Short-Circuit Protection
      9. 7.3.9  Soft Start
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 CCM Mode
      4. 7.4.4 Light-Load Operation (PFM Version)
      5. 7.4.5 Light-Load Operation (FPWM Version)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Set-Point
        3. 8.2.2.3 Switching Frequency
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Output Capacitor Selection
        6. 8.2.2.6 Input Capacitor Selection
        7. 8.2.2.7 Bootstrap Capacitor
        8. 8.2.2.8 Undervoltage Lockout Setpoint
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Compact Layout for EMI Reduction
        2. 8.4.1.2 Feedback Resistors
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

Figure 5-1 12-Pin WSONDRR Package(Top View)
Table 5-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO
SW1, 2, 3PSwitching output of the converter. Internally connected to source of the high-side FET and drain of the low-side FET. Connect to power inductor.
BOOT4PBootstrap capacitor connection for high-side FET driver. Connect a high quality 100nF capacitor from this pin to the SW pin.
PG5AOpen-drain power-good monitor output that asserts low if the FB voltage is not within the specified window thresholds. A 10kΩ to 100kΩ pull up resistor to a suitable voltage is required. If not used, PG can be left open or connected to GND.

RT

6

A

Frequency setting pin used to set the switching frequency between 200kHz and by placing an external resistor from RT to AGND. RT open defaults to 440kHz and RT short to ground defaults to 1MHz.
FB7AFeedback input to the converter. Connect a resistor divider to set the output voltage. Never short this terminal to ground during operation.

AGND

8

G

Analog ground. Zero-voltage reference for internal references and logic. All electrical parameters are measured with respect to this pin. These pins must be connected to PGND using a small net-tie.
EN9APrecision enable input pin. High = On, Low = Off. Can be connected to VIN. Precision enable allows the pin to be used as an adjustable input voltage UVLO. Connect an external resistor divider between this pin, VIN and AGND to create an external UVLO. Do not float.
VIN10, 11, 12PInput supply voltage. Connect the input supply to these pins. Connect input capacitors CIN between these pins and PGND in close proximity to the device.
PGND

13

GPower ground terminals, connected to the source of low-side FET internally. Connect to system ground, ground side of CIN and COUT. Path to CIN must be as short as possible.
(1) A = Analog, P = Power, G = Ground.