SNAS879 December   2024 LMR60420

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Undervoltage Lockout (UVLO)
      2. 7.3.2 Soft Start and Recovery from Dropout
      3. 7.3.3 Frequency Selection With RT
      4. 7.3.4 MODE/SYNC Pin Control
      5. 7.3.5 Output Voltage Selection
      6. 7.3.6 Current Limit
      7. 7.3.7 Hiccup Mode
      8. 7.3.8 Power-Good Function
      9. 7.3.9 Spread Spectrum
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Continuous Conduction Mode (CCM)
        2. 7.4.2.2 Auto Mode - Light Load Operation
        3. 7.4.2.3 FPWM Operation - Light Load Operation
        4. 7.4.2.4 Minimum On-Time
        5. 7.4.2.5 Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching Frequency Selection
        2. 8.2.2.2 Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Input Capacitor Selection
        5. 8.2.2.5 Bootstrap Capacitor (CBOOT) Selection
        6. 8.2.2.6 FB Voltage Divider for Adjustable Output Voltages
          1. 8.2.2.6.1 Feedforward Capacitor (CFF) Selection
        7. 8.2.2.7 RPG - PG Pullup Resistor
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Ground and Thermal Plane Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.8 Power-Good Function

The power-good function of the LMR60420 can be used to reset a system microprocessor whenever the output voltage is out of regulation or to facilitate power sequencing of down stream components. This feature is an optional feature that is implemented by including a pullup resistor between the PG pin and an excellent voltage supply. Refer to Section 6.3 for the recommended range of pullup reference voltage.

The power-good output is valid after the soft-start sequence has completed and after the input voltage has risen above VIN(PG-VALID). After both of these conditions are met, the voltage between PG and GND indicates whether the output voltage is within regulation or not. A logic HIGH signal indicates that the output voltage is within regulation while a logic LOW signal represents that the output voltage is not in regulation. A deglitch filter has been included to make sure that spurious glitches on the output voltage do not effect the PG pin output.

The PG pin is pulled low under the following conditions:

  • Output voltage is higher than the PGOOD over-voltage rising threshold (VPG-OVP(R)) for a duration of at least tPG-DEGLITCH
  • Output voltage falls lower than the PGOOD under-voltage falling threshold (VPG-UV(F)) for a duration of at least tPG-DEGLITCH

After the PG pin has been pulled low following a fault condition at the output, the PG pin voltage must remain low for at least tPG-DEASSERT or about 2ms (typical). After tPG-DEASSERT has passed, one of the following conditions must be satisfied for the PG pin voltage to be pulled up:

  • Assuming recovery form an undervoltage fault, the output voltage must rise higher than the PGOOD undervoltage rising threshold (VPG-UV(R)) and remain below the over-voltage rising threshold (VPG-OVP(R)) for a duration of at least tPG-DEGLITCH.
  • Assuming recovery from an overvoltage fault, the output voltage must fall lower than the PGOOD overvoltage falling threshold (VPG-OVP(F)) and remain above the undervoltage falling threshold for a duration of at least tPG-DEGLITCH.
LMR60420 Power-Good Thresholds Figure 7-5 Power-Good Thresholds