SNAS877 December   2024 LMR60440

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Undervoltage Lockout (UVLO)
      2. 7.3.2 Soft Start and Recovery from Dropout
      3. 7.3.3 Frequency Selection With RT
      4. 7.3.4 MODE/SYNC Pin Control
      5. 7.3.5 Output Voltage Selection
      6. 7.3.6 Current Limit
      7. 7.3.7 Hiccup Mode
      8. 7.3.8 Power-Good Function
      9. 7.3.9 Spread Spectrum
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Continuous Conduction Mode (CCM)
        2. 7.4.2.2 Auto Mode - Light Load Operation
        3. 7.4.2.3 FPWM Operation - Light Load Operation
        4. 7.4.2.4 Minimum On-Time
        5. 7.4.2.5 Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching Frequency Selection
        2. 8.2.2.2 Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Input Capacitor Selection
        5. 8.2.2.5 Bootstrap Capacitor (CBOOT) Selection
        6. 8.2.2.6 FB Voltage Divider for Adjustable Output Voltages
          1. 8.2.2.6.1 Feedforward Capacitor (CFF) Selection
        7. 8.2.2.7 RPG - PG Pullup Resistor
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Ground and Thermal Plane Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.3 Output Capacitor Selection

The peak current mode control scheme of the LMR60440 device allows operation over a wide range of inductor and output capacitor combinations. The output capacitance is responsible for maintaining the desired output voltage during operation. The output capacitance impacts several key performance factors including:

  • The amount of output voltage ripple during steady state operation
  • The overshoot and undershoot of the output voltage when a load transient occurs
  • Loop stability

During steady state operation, the inductor supplies a triangular current to the load. The AC portion of this triangular current is filtered out by the output capacitance while the DC portion passes through to the load. The AC current through the output capacitance and the equivalent series resistance (ESR) of this capacitance both contribute to the output voltage ripple. Equation 10 can be used to estimate the amount of peak to peak output voltage ripple required for a given output capacitance:

Equation 10. Vripple≅∆IL×ESR2+18×fsw×COUT2

Where:

  • ΔIL = the peak to peak inductor current

The output capacitance is responsible for maintaining the output voltage during transient conditions in the load current. To determine the output capacitance and ESR required for a desired output voltage transient Equation 11, Equation 12, and Equation 13 can be used:

Equation 11. COUT≥∆IOUTfSW×∆VOUT×K×1-D×1+K+K212×2-D
Equation 12. ESR≤2+K×∆VOUT2×∆IOUT×1+K+K212×1+11-D
Equation 13. D=VOUTVIN

Where:

  • ΔVOUT = output voltage transient
  • ΔIOUT = output current transient
  • K = inductor current ripple factor

The output capacitance is also important for overall loop stability and careful study must be done with the selected capacitance to confirm adequate phase margin and transient performance.

In this example, a single 22μF multilayer ceramic capacitor is used.