JAJSR66 September   2024 LMR66430-EP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable, Start-Up, and Shutdown
      2. 7.3.2  External CLK SYNC (with MODE/SYNC)
        1. 7.3.2.1 Pulse-Dependent MODE/SYNC Pin Control
      3. 7.3.3  Adjustable Switching Frequency (with RT)
      4. 7.3.4  Power-Good Output Operation
      5. 7.3.5  Internal LDO, VCC, and VOUT/FB Input
      6. 7.3.6  Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      7. 7.3.7  Output Voltage Selection
      8. 7.3.8  Spread Spectrum
      9. 7.3.9  Soft Start and Recovery from Dropout
        1. 7.3.9.1 Recovery from Dropout
      10. 7.3.10 Current Limit and Short Circuit
      11. 7.3.11 Thermal Shutdown
      12. 7.3.12 Input Supply Current
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 Auto Mode – Light Load Operation
          1. 7.4.3.2.1 Diode Emulation
          2. 7.4.3.2.2 Frequency Reduction
        3. 7.4.3.3 FPWM Mode – Light Load Operation
        4. 7.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 LMR66430-EP Design Guide
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1  Choosing the Switching Frequency
        2. 8.2.3.2  Setting the Output Voltage
        3. 8.2.3.3  Inductor Selection
        4. 8.2.3.4  Output Capacitor Selection
        5. 8.2.3.5  Input Capacitor Selection
        6. 8.2.3.6  CBOOT
        7. 8.2.3.7  VCC
        8. 8.2.3.8  CFF Selection
        9. 8.2.3.9  External UVLO
        10. 8.2.3.10 Maximum Ambient Temperature
      4. 8.2.4 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground and Thermal Considerations
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature range of –55°C to +150°C, unless otherwise noted. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 13.5V, VOUT = 3.3V. 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
VINMIN Input voltage rising threshold for start-up Before start-up 3.2 3.35 3.5 V
Input voltage falling threshold Once operating 2.45 2.7 3 V
ISD(VIN) Shutdown quiescent current at VIN pin EN = 0V 0.25 1 µA
IBIAS Non-switching input current at VOUT/FB Fixed 3.3Vout, VVOUT/FB = 3.47V 4.2 6.5 µA
IQVIN(nonsw) Non-switching input current; measured at VIN pin (1) Fixed 3.3V VOUT, VVOUT/FB = 3.47V 1.2 2.3 µA
ENABLE (EN PIN)
VEN-WAKE EN wakeup threshold 0.5 0.7 1 V
VEN-VOUT Precision enable rising threshold for VOUT 1.16 1.23 1.3 V
VEN-HYST Enable hysteresis below VEN-VOUT 0.3 0.35 0.4 V
ILKG-EN Enable pin input leakage current VEN = VIN = 13.5V 10 nA
INTERNAL LDO (VCC PIN)
VCC VCC pin output voltage VFB = 0V, IVCC = 1mA 3.1 3.3 3.45 V
VOLTAGE FEEDBACK (VOUT/FB PIN)
VOUT Output voltage accuracy for fixed VOUT 3.3V VOUT, VIN = 3.6V to 36V, FPWM mode 3.27 3.3 3.32 V
VFB Internal reference voltage accuracy VOUT = 1V, VIN = 3.0V to 36V, FPWM Mode 0.99 1.00 1.01 V
IFB(LKG) FB input current Adjustable configuration, FB = 1V 10 nA
CURRENT LIMITS
IPEAKMAX High-side peak current limit 3.8 4.4 5 A
IVALMAX Low-side valley current limit 2.9 3.5 4 A
IPEAKMIN Minimum peak current limit Auto mode 0.45 0.69 0.95 A
INEGMIN Low-side valley current negative limit FPWM mode –1.5 –1.3 –1 A
IZC Zero-cross current limit Auto mode 30 80 135 mA
POWER GOOD (PG PIN)
PGOV PG upper threshold - rising % of VOUT/FB (Fixed or Adj. output) 104 108 111 %
PGUV PG upper threshold - falling % of VOUT/FB (Fixed or Adj. output) 89 91 94.2 %
PGHYST PG recovery hysteresis for OV % of VOUT/FB target regulation voltage 1.7 2 2.3 %
PG recovery hysteresis for UV % of VOUT/FB target regulation voltage 1.9 3.3 4.6 %
VPG-VAL Minimum VIN for PG function VEN = 0V, RPG_PU = 10kΩ 1.5 V
RPG PG ON resistance VEN = 3.3V, 200µA pullup current 100 Ω
RPG PG ON resistance VEN = 0V, 200µA pullup current 100 Ω
tRESET_FILTER PG deglitch delay at falling edge 25 40 75 µs
tPG_ACT Delay time to PG high signal 1.35 2.5 4 ms
SOFT START
tSS Time from first SW pulse to VOUT/FB at 90% of set point 2 3.5 4.6 ms
tHICCUP Time in hiccup before retry soft start 30 50 75 ms
OSCILLATOR (SYNC/MODE PIN)
tPULSE_H_ATE High level pulse minimum duration needed to be recognized as a valid clock signal (2) 100 ns
tPULSE_L_ATE Low level pulse minimum duration needed to be recognized as a valid clock signal (2) 100 ns
tSYNC_THRESH High/Low level pulse maximum duration to be recognized as a valid clock signal 6 9 12.5 µs
FSW(1MHz) Switching Frequency with fixed 1 MHz 900 1000 1060 kHz
VMODE_L SYNC/MODE input voltage low level threshold 1 V
VMODE_H SYNC/MODE input voltage high level threshold 1.65 V
OSCILLATOR (RT PIN)
FSW(1MHz) Switching frequency with Internal fixed 1 MHz setting RT pin tied to VCC 900 1000 1060 kHz
FSW(2p2MHz) Switching frequency with fixed 2.2MHz RT pin tied to GND 2050 2200 2350 kHz
FSW(Adj) Accuracy of external frequency, 400kHz RRT = 39.2kΩ 0.1% resistor 340 400 460 kHz
SWITCH NODE
tON-MIN Minimum HS switch on-time FPWM mode IOUT = 1A, 2.2MHz fixed 65 76 ns
tOFF-MIN Minimum HS switch off-time 60 85 ns
tON-MAX Maximum HS switch on-time HS timeout in dropout 6 9 13 µs
POWER STAGE
VBOOT_UVLO Voltage on BOOT pin compared to SW which will turnoff high-side switch 2.1 V
RDSON-HS High-side MOSFET on-resistance Load = 1A 132 260 mΩ
RDSON-LS Low-side MOSFET on-resistance Load = 1A 75 140 mΩ
(1) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
(2) The high/low level clock pulse duration must be equal to or greater than the value shown.