JAJSDW2C November   2016  – August 2021 LMS3635-Q1 , LMS3655-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Tables
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Thermal Information (for Device Mounted on PCB)
    6. 7.6 Electrical Characteristics
    7. 7.7 System Characteristics
    8. 7.8 Timing Requirements
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 Control Scheme
    3. 8.3 Feature Description
      1. 8.3.1 RESET Flag Output
      2. 8.3.2 Enable and Start-Up
      3. 8.3.3 Soft-Start Function
      4. 8.3.4 Current Limit
      5. 8.3.5 Hiccup Mode
      6. 8.3.6 Synchronizing Input
      7. 8.3.7 Undervoltage Lockout (UVLO) and Thermal Shutdown (TSD)
      8. 8.3.8 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 AUTO Mode
      2. 8.4.2 FPWM Mode
      3. 8.4.3 Dropout
      4. 8.4.4 Spread-Spectrum Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 General Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 External Components Selection
            1. 9.2.1.2.2.1 Input Capacitors
            2. 9.2.1.2.2.2 Output Inductors and Capacitors
              1. 9.2.1.2.2.2.1 Inductor Selection
              2. 9.2.1.2.2.2.2 Output Capacitor Selection
          3. 9.2.1.2.3 Setting the Output Voltage
          4. 9.2.1.2.4 FB for Adjustable Output
          5. 9.2.1.2.5 VCC
          6. 9.2.1.2.6 BIAS
          7. 9.2.1.2.7 CBOOT
          8. 9.2.1.2.8 Maximum Ambient Temperature
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Fixed 5-V Output for USB-Type Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Fixed 3.3-V Output
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
      4. 9.2.4 6-V Adjustable Output
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
    3. 9.3 Do's and Don't's
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.4.2 Detailed Design Procedure

  • BIAS is connected to the output. This example assumes that inductive shorts are a risk for this application so a 3-Ω resistor is added between BIAS and the output. A 0.1-µF capacitor is added close to the BIAS pin.
  • FB is connected to the output through a voltage divider in order to create a voltage of 1 V at the FB pin when the output is at 6 V. A 22-pF capacitance is added in parallel with the top feedback resistor in order to improve transient behavior. BIAS and FB are connected to the output through separate traces. This is important to reduce noise and achieve good performances. See Section 11.1 for more details on the proper layout method.
  • SYNC is connected to ground directly as there is no need for this function in this application.
  • EN is toggled by an external device (like an MCU for example). A pulldown resistor is placed to ensure the part does not turn on if the external source is not driving the pin (Hi-Z condition).
  • FPWM is connected to VIN. This causes the device to operate in FPWM mode. To prevent frequency foldback behavior at low duty cycles, provide a 200mA load. In this mode, the device remains in CCM operation regardless of the output current and is ensured to be within the boundaries set by FSW. The drawback is that the efficiency is not optimized for light loads. See Section 8.4 for more details.
  • A 4.7-µF capacitor is connected between VCC and GND close to the VCC pin. This ensure stable operation of the internal LDO.
  • RESET is not used in this example so the pin has been left floating. Other possible connections can be seen in the previous typical applications and in Section 8.3.1.
  • Power components (input capacitor, output capacitor, and inductor) selection can be found here in Section 9.2.1.2.2.