JAJSE54 October   2017 LMT84-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison Tables
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Accuracy Characteristics
    6. 7.6 Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 LMT84 Transfer Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 Mounting and Thermal Conductivity
      2. 8.4.2 Output Noise Considerations
      3. 8.4.3 Capacitive Loads
      4. 8.4.4 Output Voltage Shift
  9. 9 Application and Implementation
    1. 9.1 Applications Information
    2. 9.2 Typical Applications
      1. 9.2.1 Connection to an ADC
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Conserving Power Dissipation With Shutdown
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Applications Information

The LMT84-Q1 features make it suitable for many general temperature-sensing applications. It can operate down to 1.5-V supply with 5.4-µA power consumption, making it ideal for battery-powered devices.

9.2 Typical Applications

9.2.1 Connection to an ADC

LMT84-Q1 suggested_conn_sampling_analog_to_digital_nis167.gif Figure 12. Suggested Connection to a Sampling Analog-to-Digital Converter Input Stage

9.2.1.1 Design Requirements

Most CMOS ADCs found in microcontrollers and ASICs have a sampled data comparator input structure. When the ADC charges the sampling cap, it requires instantaneous charge from the output of the analog source such as the LMT84-Q1 temperature sensor and many op amps. This requirement is easily accommodated by the addition of a capacitor (CFILTER).

9.2.1.2 Detailed Design Procedure

The size of CFILTER depends on the size of the sampling capacitor and the sampling frequency. Because not all ADCs have identical input stages, the charge requirements will vary. This general ADC application is shown as an example only.

9.2.1.3 Application Curve

LMT84-Q1 C001_SNIS167.png Figure 13. Analog Output Transfer Function

9.2.2 Conserving Power Dissipation With Shutdown

LMT84-Q1 conversing_power_dissipation_with_shutdown_nis167.gif Figure 14. Simple Shutdown Connection of the LMT84-Q1

9.2.2.1 Design Requirements

Because the power consumption of the LMT84-Q1 is less than 9 µA, it can simply be powered directly from any logic gate output and therefore not require a specific shutdown pin. The device can even be powered directly from a microcontroller GPIO. In this way, it can easily be turned off for cases such as battery-powered systems where power savings are critical.

9.2.2.2 Detailed Design Procedure

Simply connect the VDD pin of the LMT84-Q1 directly to the logic shutdown signal from a microcontroller.

9.2.2.3 Application Curves

LMT84-Q1 LMT84_SNIS167_3p3_nl_resptim.png

INDENT:

Time: 500 µs/div; Top trace: VDD 1 V/div;
Bottom trace: OUT 1 V/div
Figure 15. Output Turnon Response Time Without a Capacitive Load and VDD= 3.3 V
LMT84-Q1 LMT84_SNIS167_3p3_1nf_resptim.png

INDENT:

Time: 500 µs/div; Top trace: VDD 1 V/div;
Bottom trace: OUT 1 V/div
Figure 17. Output Turnon Response Time With 1.1-Nf Capacitive Load and VDD= 3.3 V
LMT84-Q1 LMT84_SNIS167_5p0_nl_resptim.png

INDENT:

Time: 500 µs/div; Top trace: VDD 2 V/div;
Bottom trace: OUT 1 V/div
Figure 16. Output Turnon Response Time Without a Capacitive Load and VDD= 5 V
LMT84-Q1 LMT84_SNIS167_5p0_1nf_resptim.png

INDENT:

Time: 500 µs/div; Top trace: VDD 2 V/div;
Bottom trace: OUT 1 V/div
Figure 18. Output Turnon Response Time With 1.1-Nf Capacitive Load and VDD= 5 V