JAJS988H April   2002  – June 2016 LMV341-N , LMV342-N , LMV344-N

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - 2.7 V (DC)
    6. 6.6 Electrical Characteristics - 2.7 V (AC)
    7. 6.7 Electrical Characteristics - 5 V (DC)
    8. 6.8 Electrical Characteristics - 5 V (AC)
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Class AB Turnaround Stage Amplifier
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Feature
      2. 7.4.2 Low Input Bias Current
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Sample and Hold Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 関連リンク
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 コミュニティ・リソース
    6. 11.6 商標
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DCK Package
6-Pin SC70
Top View
LMV341-N LMV342-N LMV344-N sc70_diag.gif

Pin Functions – LMV341-N

PIN TYPE(1) DESCRIPTION
NAME NO.
+IN 1 I Noninverting input
–IN 3 I Inverting input
GND 2 P Negative supply input
OUT 4 O Output
V+ 6 P Positive supply input
SHDN 5 I Active low enable input
(1) I = Input, O = Output, and P = Power
DGK or D Package
8-Pin VSSOP or SOIC
Top View
LMV341-N LMV342-N LMV344-N 20030451.png

Pin Functions – LMV342-N

PIN TYPE(1) DESCRIPTION
NAME NO.
IN A+ 3 I Noninverting input, channel A
IN A– 2 I Inverting input, channel A
IN B+ 5 I Noninverting input, channel B
IN B– 6 I Inverting input, channel B
OUT A 1 O Output, channel A
OUT B 7 O Output, channel B
V+ 8 P Positive (highest) power supply
V– 4 P Negative (lowest) power supply
(1) I = Input, O = Output, and P = Power
PW or D Package
14-Pin TSSOP or SOIC
Top View
LMV341-N LMV342-N LMV344-N 20030452.png

Pin Functions – LMV344-N

PIN TYPE(1) DESCRIPTION
NAME NO.
IN A+ 3 I Noninverting input, channel A
IN A– 2 I Inverting input, channel A
IN B+ 5 I Noninverting input, channel B
IN B– 6 I Inverting input, channel B
IN C+ 10 I Noninverting input, channel C
IN C– 9 I Inverting input, channel C
IN D+ 12 I Noninverting input, channel D
IN D– 13 I Inverting input, channel D
OUT A 1 O Output, channel A
OUT B 7 O Output, channel B
OUT C 8 O Output, channel C
OUT D 14 O Output, channel D
V+ 4 P Positive (highest) power supply
V– 11 P Negative (lowest) power supply
(1) I = Input, O = Output, and P = Power