6 Specifications
6.1 Absolute Maximum Ratings
See (1)(2)(3).
|
MIN |
MAX |
UNIT |
Supply voltage |
|
6 |
V |
Voltage at input / output pin |
GND − 0.3 |
6 |
V |
Output current |
|
10 |
mA |
Total package current |
|
50 |
mA |
Junction temperature(4) |
|
150 |
°C |
Storage temperature, Tstg |
–65 |
150 |
°C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and specifications.
(3) For soldering specifications, see
Absolute Maximum Ratings for Soldering (
SNOA549).
(4) The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.
6.2 ESD Ratings
|
VALUE |
UNIT |
V(ESD) |
Electrostatic discharge |
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) |
±2000 |
V |
Machine model |
±200 |
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
6.3 Recommended Operating Conditions
|
MIN |
MAX |
UNIT |
Supply voltage |
2.2 |
5.5 |
V |
Junction temperature(1) |
–40 |
125 |
°C |
(1) The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.
6.4 Thermal Information
THERMAL METRIC(1) |
LMV7231 |
UNIT |
RTW (WQFN) |
24 PINS |
RθJA |
Junction-to-ambient thermal resistance |
37.4 |
°C/W |
RθJC(top) |
Junction-to-case (top) thermal resistance |
40.2 |
°C/W |
RθJB |
Junction-to-board thermal resistance |
16.1 |
°C/W |
ψJT |
Junction-to-top characterization parameter |
0.6 |
°C/W |
ψJB |
Junction-to-board characterization parameter |
16.2 |
°C/W |
RθJC(bot) |
Junction-to-case (bottom) thermal resistance |
5.2 |
°C/W |
(1) For more information about traditional and new thermal metrics, see the
Semiconductor and IC Package Thermal Metrics application report,
SPRA953.
6.5 3.3-V Electrical Characteristics
Unless otherwise specified, all limits ensured for TA = 25°C, V+ = 3.3 V ±10%, GND = 0 V, and RL > 1 MΩ.
PARAMETER |
TEST CONDITION |
MIN(1) |
TYP(2) |
MAX(1) |
UNIT |
VTHR |
Threshold: input rising |
RL = 10 kΩ |
|
394 |
400 |
406 |
mV |
TA = –10°C to +70°C |
391.4 |
|
408.6 |
VTHF |
Threshold: input falling |
RL = 10 kΩ |
|
386 |
394 |
401 |
mV |
TA = –10°C to +70°C |
383.8 |
|
403.2 |
VHYST |
Hysteresis (VTHR − VTHF) |
RL = 10 kΩ |
3.9 |
6.0 |
8.8 |
mV |
IBIAS |
Input bias current |
VIN = V+, GND, and 5.5 V |
|
–5 |
0.05 |
5 |
nA |
TA = –10°C to +70°C |
–15 |
|
15 |
VOL |
Output low voltage |
IL = 5 mA |
|
|
160 |
200 |
mV |
TA = –10°C to +70°C |
|
|
250 |
IOFF |
Output leakage current |
VOUT = V+, 5.5 V and 40 mV of overdrive |
|
|
|
0.4 |
μA |
TA = –10°C to +70°C |
|
|
1 |
tPDHL1 |
High-to-low propagation delay (+IN falling) |
10 mV of overdrive |
|
2.6 |
6 |
μs |
tPDHL2 |
High-to-low propagation delay (-IN rising) |
10 mV of overdrive |
|
5.4 |
10 |
μs |
tPDLH1 |
Low-to-high propagation delay (+IN rising) |
10 mV of overdrive |
|
5.6 |
10 |
μs |
tPDLH2 |
Low-to-high propagation delay (-IN falling) |
10 mV of overdrive |
|
2.8 |
6 |
μs |
tr |
Output rise time |
CL= 10 pF, RL= 10 kΩ |
|
0.5 |
|
μs |
tf |
Output fall time |
CL = 100 pF, RL = 10 kΩ |
|
|
|
0.25 |
μs |
TA = –10°C to +70°C |
|
|
0.3 |
IIN(1) |
Digital input logic 1 leakage current |
|
|
|
0.2 |
μA |
TA = –10°C to +70°C |
|
|
1 |
IIN(0) |
Digital input logic 0 leakage current |
|
|
|
0.2 |
μA |
TA = –10°C to +70°C |
|
|
1 |
VIH |
Digital input logic 1 voltage |
TA = –10°C to +70°C |
0.7 × V+ |
|
|
V |
VIL |
Digital input logic 0 voltage |
TA = –10°C to +70°C |
|
|
0.3 × V+ |
V |
IS |
Power supply current |
No loading (outputs high) |
|
|
46 |
60 |
μA |
TA = –10°C to +70°C |
|
|
84 |
VTHPSS |
VTH power supply sensitivity(3) |
V+ ramp rate = 1.1 ms V+ step = 2.5 V to 4.5 V |
|
|
400 |
μV |
V+ ramp rate = 1.1 ms V+ step = 4.5 V to 2.5 V |
–400 |
|
|
μV |
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the Statistical Quality Control (SQC) method.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depends on the application and configuration. The typical values are not tested and are not ensured on shipped production material.
(3) VTH power supply sensitivity is defined as the temporary shift in the internal voltage reference due to a step on the V+ pin.
6.6 Typical Characteristics
V+ = 3.3 V and TA =25°C unless otherwise noted.
Figure 1. +IN Input Rising Threshold Distribution
Figure 3. +IN Input Falling Threshold Distribution
Figure 5. +IN Hysteresis Distribution
Figure 7. Input Rising Threshold Voltage vs Temperature
Figure 9. Input Falling Threshold Voltage vs Temperature
Figure 11. Hysteresis vs Temperature
Figure 13. Supply Current vs Supply Voltage and Temperature
Figure 15. Supply Current vs Output Sink Current
Figure 17. Supply Current vs Output Sink Current
Figure 19. Bias Current vs Input Voltage
Figure 21. Output Voltage Low vs Output Sink Current
Figure 23. Output Voltage Low vs Output Sink Current
Figure 25. Output Short Circuit Current vs Output Voltage
Figure 27. Propagation Delay vs Input Overdrive
Figure 29. Propagation Delay
Figure 31. Output Leakage Current vs Output Voltage
Figure 2. −IN Input Rising Threshold Distribution
Figure 4. −IN Input Falling Threshold Distribution
Figure 6. −IN Hysteresis Distribution
Figure 8. Input Rising Threshold Voltage vs Supply Voltage
Figure 10. Input Falling Threshold Voltage vs Supply Voltage
Figure 12. Hysteresis vs Supply Voltage
Figure 14. Supply Current vs Output Sink Current
Figure 16. Supply Current vs Output Sink Current
Figure 18. Bias Current vs Input Voltage
Figure 20. Bias Current vs Input Voltage
Figure 22. Output Voltage Low vs Output Sink Current
Figure 24. Output Voltage Low vs Output Sink Current
Figure 26. Output Short Circuit Current vs Output Voltage
Figure 28. Rise and Fall Times vs Output Pullup Resistor
Figure 30. Output Leakage Current vs Output Voltage