8.2.1 Square Wave Oscillator

Figure 27. Square Wave Oscillator Application

8.2.1.2 Detailed Design Procedure

To analyze the circuit, consider it when the output is high. That implies that the inverted input (V_C) is lower than the Non-Inverting input (V_A).

Figure 28. Squarewave Oscillator Timing Thresholds

This causes the C₁ to get charged through R_4, and the voltage V_C increases till it is equal to the Non-Inverting input. The value of V_A at this point is

Equation 9.

If R₁ = R₂ = R₃, then V_A1 = 2V_CC/3

At this point the comparator switches pulling down the output to the negative rail. The value of V_A at this point is

Equation 10.

If R₁ = R₂ = R₃, then V_A2 = V_CC/3

The capacitor C₁ now discharges through R₄, and the voltage V_C decreases till it is equal to V_A2, at which point the comparator switches again, bringing it back to the initial stage. The time period is equal to twice the time it takes to discharge C₁ from 2V_CC/3 to V_CC/3, which is given by R₄C₁.ln2. Hence the formula for the frequency is:

F = 1/(2·R₄·C₁·ln2)

8.2.1.3 Application Curve

Figure 29 shows the simulated results of an oscillator using the following values:

1. R₁ = R₂ = R₃ = R₄ = 100 kΩ
2. C₁ = 750 pF, C_L = 20 pF
3. V+ = 5 V, V- = GND
4. C_STRAY (not shown) from Va to GND = 10 pF

Figure 29. Square Wave Oscillator Output Waveforms

8.2.2 Positive Peak Detector

Figure 30. Positive Peak Detector

The positive peak detector is basically the comparator operated as a unity gain follower with a large holding capacitor from the output to ground. A transistor is added to the output to provide a low impedance current source. The upper output swing is limited by the emitter-base forward voltage. This allows capture of the most positive input signal between 0 V and (V+) - 0.7V.

When the output of the comparator goes high, current is passed through the transistor to charge up the capacitor. The only discharge path will be the 1-MΩ resistor shunting C1 and any load that is connected to the output. The decay time can be altered simply by changing the 1-MΩ resistor.

8.2.3 Negative Peak Detector

Figure 31. Negative Peak Detector for Negative Supply

The Negative Peak Detector circuit will store the peak negative voltage below ground ( 0 V to V-). For the negative detector, the output transistor acts as a low-impedance current sink.

When V_IN is more negative than V_OUT, the output transistor will conduct and pull the output to -V_CC, charging C1. Charging stops when C₁ reaches the same level as V_IN. Because there is no pull-up resistor, the only discharge path will be the 1-MΩ resistor and any load impedance applied. Therefore, the decay time is set by varying the 1-MΩ resistor. Be sure to observe the polarity of C₁!

Figure 32. Negative Peak Detector for Positive Supply

An alternate positive supply version is shown in Figure 32 that will capture the lowest applied V_IN value between V+ and ground (V+ to 0V).

The output of either version should be buffered by a high-impedance follower stage to prevent loading of the RC circuit.

8.2.4 Window Detector

Figure 33. Window Detector

A window detector monitors the input signal to determine if it falls between two voltage levels. Both outputs are true (high) when V_REF1 < V_IN < V_REF2

Figure 34. Window Detector Output Signal

The comparator outputs A and B are high only when V_REF1 < V_IN < V_REF2, or within the window, where these are defined as:

To determine if the input signal falls outside of the two voltage levels, both inputs on each comparators can be reversed to invert the logic.

The outputs should be tied together and use a shared pull-up resistor for a common logic output. If individual limit outputs are needed, then each output will require it's own pull-up resistor.

Other names for window detectors are: threshold detector, level detector, and amplitude trigger or detector.