JAJSMF0B July 2021 – February 2024 LMX1204
PRODUCTION DATA
The SYSREF outputs within the clock output channels have the same output buffer structure as the clock output buffer, with the addition of circuitry to adjust the common-mode voltage. The SYSREF outputs are CML outputs with a common-mode voltage that can be adjusted with the SYSREFOUTx_VCM field, and the output level that can be programmed with the SYSREFOUTx_PWR field. This feature is to allow DC coupling. Note that the CLKOUT outputs do not have adjustable common-mode voltage and must be AC coupled for optimal noise performance.
The common-mode voltage and output power are interrelated and can be simulated assuming a 100Ω differential load and no DC path to ground. The common mode voltage and output are interrelated as shown in Table 6-9. As there is a restriction required for long term reliability that VCM – VOD/2 ≥ 0.5 V combinations of VCM and VOD that do not satisfy this constraint are excluded from the table.
SYSREFOUTx_PWR | SYSREFOUTx_VCM | VOD | VCM |
---|---|---|---|
0 | 0 | 0.31 | 0.91 |
1 | 0.31 | 1.06 | |
2 | 0.31 | 1.23 | |
3 | 0.32 | 1.41 | |
4 | 0.32 | 1.58 | |
5 | 0.33 | 1.75 | |
6 | 0.33 | 1.94 | |
7 | 0.34 | 2.11 | |
1 | 0 | 0.34 | 0.59 |
1 | 0.35 | 0.76 | |
2 | 0.35 | 0.96 | |
3 | 0.35 | 1.19 | |
4 | 0.36 | 1.39 | |
5 | 0.36 | 1.59 | |
6 | 0.36 | 1.82 | |
7 | 0.36 | 2.03 | |
2 | 0 | 0.39 | 0.46 |
1 | 0.42 | 0.52 | |
2 | 0.44 | 0.69 | |
3 | 0.46 | 0.96 | |
4 | 0.46 | 1.2 | |
5 | 0.47 | 1.43 | |
6 | 0.48 | 1.7 | |
7 | 0.49 | 1.94 | |
3 | 2 | 0.48 | 0.53 |
3 | 0.51 | 0.74 | |
4 | 0.53 | 1.02 | |
5 | 0.54 | 1.27 | |
6 | 0.55 | 1.59 | |
7 | 0.56 | 1.87 | |
4 | 3 | 0.56 | 0.59 |
4 | 0.59 | 0.83 | |
5 | 0.61 | 1.13 | |
6 | 0.62 | 1.47 | |
7 | 0.64 | 1.79 | |
5 | 3 | 0.58 | 0.54 |
4 | 0.64 | 0.69 | |
5 | 0.67 | 0.98 | |
6 | 0.69 | 1.37 | |
7 | 0.71 | 1.72 | |
6 | 5 | 0.73 | 0.84 |
6 | 0.75 | 1.26 | |
7 | 0.78 | 1.64 | |
7 | 5 | 0.78 | 0.73 |
6 | 0.82 | 1.15 | |
7 | 0.84 | 1.57 |