SNAS850 December   2024 LMX1205

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Input
        1. 6.3.3.1 Clock Input Adjustable Delay
      4. 6.3.4 Clock Outputs
        1. 6.3.4.1 Clock Output Buffers
        2. 6.3.4.2 Clock Output Adjustable Delay
        3. 6.3.4.3 Clock MUX
        4. 6.3.4.4 Clock Divider
        5. 6.3.4.5 Clock Multiplier
          1. 6.3.4.5.1 General Information About the Clock Multiplier
          2. 6.3.4.5.2 State Machine Clock for the Clock Multiplier
            1. 6.3.4.5.2.1 State Machine Clock
          3. 6.3.4.5.3 Calibration for the Clock Multiplier
          4. 6.3.4.5.4 Lock Detect for the Clock Multiplier
      5. 6.3.5 LOGICLK Outputs
        1. 6.3.5.1 LOGICLK Output Format
        2. 6.3.5.2 LOGICLK Dividers
      6. 6.3.6 SYSREF
        1. 6.3.6.1 SYSREF Output Buffers
          1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.6.1.2 LOGISYSREF Output Buffer
          3. 6.3.6.1.3 SYSREF Frequency and Delay Generation
          4. 6.3.6.1.4 SYSREFREQ Pins and SYSREFREQ SPI Controlled Fields
            1. 6.3.6.1.4.1 SYSREFREQ Pins Common-Mode Voltage
            2. 6.3.6.1.4.2 SYSREFREQ Windowing Feature
              1. 6.3.6.1.4.2.1 General Procedure Flowchart for SYSREF Windowing Operation
              2. 6.3.6.1.4.2.2 Other Guidance For SYSREF Windowing
              3. 6.3.6.1.4.2.3 For Glitch-Free Output
              4. 6.3.6.1.4.2.4 If Using SYNC Feature
              5. 6.3.6.1.4.2.5 SYNC Feature
      7. 6.3.7 Power-Up Timing
      8. 6.3.8 Treatment of Unused Pins
    4. 6.4 Device Functional Modes Configurations
  8. 7 Register Map
    1. 7.1 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Reference
      1. 8.1.1 Typical Application
        1. 8.1.1.1 Design Requirements
        2. 8.1.1.2 Detailed Design Procedure
        3. 8.1.1.3 Application Plots
    2. 8.2 Power Supply Recommendations
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
6.3.4.5.2.1 State Machine Clock

A valid state machine clock is required (SMCLK_EN=1 and signal present at CLKIN pins) in below circumstances:

  1. Multiplier is being calibrated.
  2. Lock Detect from the multiplier is being monitored.
  3. Clock divide value is being changed to 6 or 8.
  4. For the device to perform a proper power on reset.
    1. Note that SMCLK_EN=1 is enabled by the power on reset, but an input clock is also required to allow the power on reset before SMCLK_EN can be set to 0.

When the state machine clock is enabled, the clock needs to be less than 30MHz and the frequency is as follows:

fSMCLK = fCLKIN / (SMCLK_DIV_PRE * SMCLK_DIV)

When the state machine clock is not required, the clock can be disabled by setting SMCLK_EN=0 to minimize crosstalk and spurs.