SNAS850 December   2024 LMX1205

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Input
        1. 6.3.3.1 Clock Input Adjustable Delay
      4. 6.3.4 Clock Outputs
        1. 6.3.4.1 Clock Output Buffers
        2. 6.3.4.2 Clock Output Adjustable Delay
        3. 6.3.4.3 Clock MUX
        4. 6.3.4.4 Clock Divider
        5. 6.3.4.5 Clock Multiplier
          1. 6.3.4.5.1 General Information About the Clock Multiplier
          2. 6.3.4.5.2 State Machine Clock for the Clock Multiplier
            1. 6.3.4.5.2.1 State Machine Clock
          3. 6.3.4.5.3 Calibration for the Clock Multiplier
          4. 6.3.4.5.4 Lock Detect for the Clock Multiplier
      5. 6.3.5 LOGICLK Outputs
        1. 6.3.5.1 LOGICLK Output Format
        2. 6.3.5.2 LOGICLK Dividers
      6. 6.3.6 SYSREF
        1. 6.3.6.1 SYSREF Output Buffers
          1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.6.1.2 LOGISYSREF Output Buffer
          3. 6.3.6.1.3 SYSREF Frequency and Delay Generation
          4. 6.3.6.1.4 SYSREFREQ Pins and SYSREFREQ SPI Controlled Fields
            1. 6.3.6.1.4.1 SYSREFREQ Pins Common-Mode Voltage
            2. 6.3.6.1.4.2 SYSREFREQ Windowing Feature
              1. 6.3.6.1.4.2.1 General Procedure Flowchart for SYSREF Windowing Operation
              2. 6.3.6.1.4.2.2 Other Guidance For SYSREF Windowing
              3. 6.3.6.1.4.2.3 For Glitch-Free Output
              4. 6.3.6.1.4.2.4 If Using SYNC Feature
              5. 6.3.6.1.4.2.5 SYNC Feature
      7. 6.3.7 Power-Up Timing
      8. 6.3.8 Treatment of Unused Pins
    4. 6.4 Device Functional Modes Configurations
  8. 7 Register Map
    1. 7.1 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Reference
      1. 8.1.1 Typical Application
        1. 8.1.1.1 Design Requirements
        2. 8.1.1.2 Detailed Design Procedure
        3. 8.1.1.3 Application Plots
    2. 8.2 Power Supply Recommendations
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.8 Typical Characteristics

Unless stated otherwise, the following conditions can be assumed: Temperature = 25°C, Vcc = 2.5V, OUTx_PWR=6, CLKIN_N driven single ended with 10dBm at pin. Signal source used is SMA100B with ultra-low noise option B711. Phase noise analyzer is FSWP50.

LMX1205 Phase Noise Plot in Buffer Mode at 6.4GHz Output
 
Figure 5-2 Phase Noise Plot in Buffer Mode at 6.4GHz Output
LMX1205 Phase Noise Plot in Multiplier Mode at 6.4GHz Output
 
Figure 5-4 Phase Noise Plot in Multiplier Mode at 6.4GHz Output
LMX1205 Flicker Noise in Buffer Mode
 
Figure 5-6 Flicker Noise in Buffer Mode
LMX1205 Noise Floor in Divider Mode
Divider value - 2  
Figure 5-8 Noise Floor in Divider Mode
LMX1205 Single-Ended Output Power
 
Figure 5-10 Single-Ended Output Power
LMX1205 Second Harmonic in Divider Mode
Divider value: by2  
Figure 5-12 Second Harmonic in Divider Mode
LMX1205 CLKOUT Propagation Delay in Buffer Mode
 
Figure 5-14 CLKOUT Propagation Delay in Buffer Mode
LMX1205 Noise Floor wrt Input Delay Code in Buffer Mode
 
Figure 5-16 Noise Floor wrt Input Delay Code in Buffer Mode
LMX1205 Output Power wrt Input Delay Code
 
Figure 5-18 Output Power wrt Input Delay Code
LMX1205 Clock Input Delay Range
CLKIN Frequency = 9GHz  
Figure 5-20 Clock Input Delay Range
LMX1205 Clock Input Delay Step Size
 
Figure 5-22 Clock Input Delay Step Size
LMX1205 Clock Output Delay Step Size
CLKIN Frequency = 9GHz  
Figure 5-24 Clock Output Delay Step Size
LMX1205 Temperature Sensor Readback
Measured in power-down mode to make Junction Temperature = Ambient Temperature 
Figure 5-26 Temperature Sensor Readback
LMX1205 Phase Noise Plot in Divider Mode at 6.4GHz Output
 
Figure 5-3 Phase Noise Plot in Divider Mode at 6.4GHz Output
LMX1205 Noise Floor in Buffer Mode
 
Figure 5-5 Noise Floor in Buffer Mode
LMX1205 Noise Floor in Multiplier Mode
Multiplier value x2  
Figure 5-7 Noise Floor in Multiplier Mode
LMX1205 Noise Floor in Buffer Mode
 
Figure 5-9 Noise Floor in Buffer Mode
LMX1205 Second Harmonic in Buffer Mode
 
Figure 5-11 Second Harmonic in Buffer Mode
LMX1205 Second Harmonic in Multiplier Mode
Multiplier value: x2  
Figure 5-13 Second Harmonic in Multiplier Mode
LMX1205 Skew Between CLKOUT Channels
 
Figure 5-15 Skew Between CLKOUT Channels
LMX1205 Noise Floor wrt Output Delay Code in Buffer Mode
 
Figure 5-17 Noise Floor wrt Output Delay Code in Buffer Mode
LMX1205 Output Power wrt Output Delay Code
 
Figure 5-19 Output Power wrt Output Delay Code
LMX1205 Clock Input Delay Step Size
CLKIN Frequency = 9GHz  
Figure 5-21 Clock Input Delay Step Size
LMX1205 Clock Output Delay Range
CLKIN Frequency = 9GHz  
Figure 5-23 Clock Output Delay Range
LMX1205 Clock Output Delay Step Size
 
Figure 5-25 Clock Output Delay Step Size