SNAS850 December 2024 LMX1205
ADVANCE INFORMATION
The LMX1205 has four main clock outputs and one LOGICLK output. The main clock outputs are all the same frequency. This frequency can be the same, divided, or multiplied relative to the input clock. Each of these clock outputs has independent programmable power level. The LOGICLK output frequency can be divided or same frequency as clock input and has programmable output format (CML and LVDS) and power level. Second LOGICLK can be generated at LOGISYSREF output pin with the additional division of 1, 2, 4 and 8 at the LOGICLK0 path.
The SYSREF can be generated by either repeating the input from the SYSREFREQ pins, or internally generated. There is an internal SYSREF windowing feature that allows the internal timing of the device to be adjusted to optimize setup/hold times of the SYSREFREQ input with respect to the CLKIN input. This feature requires that the delay between the SYSREF edge and the next rising clock edge is consistent. Each of the five outputs has a corresponding SYSREF output that has individual programmable delays and programmable common mode. For the LOGISYSREF output, the output format is programmable as CML and LVDS.