SNAS850 December   2024 LMX1205

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Input
        1. 6.3.3.1 Clock Input Adjustable Delay
      4. 6.3.4 Clock Outputs
        1. 6.3.4.1 Clock Output Buffers
        2. 6.3.4.2 Clock Output Adjustable Delay
        3. 6.3.4.3 Clock MUX
        4. 6.3.4.4 Clock Divider
        5. 6.3.4.5 Clock Multiplier
          1. 6.3.4.5.1 General Information About the Clock Multiplier
          2. 6.3.4.5.2 State Machine Clock for the Clock Multiplier
            1. 6.3.4.5.2.1 State Machine Clock
          3. 6.3.4.5.3 Calibration for the Clock Multiplier
          4. 6.3.4.5.4 Lock Detect for the Clock Multiplier
      5. 6.3.5 LOGICLK Outputs
        1. 6.3.5.1 LOGICLK Output Format
        2. 6.3.5.2 LOGICLK Dividers
      6. 6.3.6 SYSREF
        1. 6.3.6.1 SYSREF Output Buffers
          1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.6.1.2 LOGISYSREF Output Buffer
          3. 6.3.6.1.3 SYSREF Frequency and Delay Generation
          4. 6.3.6.1.4 SYSREFREQ Pins and SYSREFREQ SPI Controlled Fields
            1. 6.3.6.1.4.1 SYSREFREQ Pins Common-Mode Voltage
            2. 6.3.6.1.4.2 SYSREFREQ Windowing Feature
              1. 6.3.6.1.4.2.1 General Procedure Flowchart for SYSREF Windowing Operation
              2. 6.3.6.1.4.2.2 Other Guidance For SYSREF Windowing
              3. 6.3.6.1.4.2.3 For Glitch-Free Output
              4. 6.3.6.1.4.2.4 If Using SYNC Feature
              5. 6.3.6.1.4.2.5 SYNC Feature
      7. 6.3.7 Power-Up Timing
      8. 6.3.8 Treatment of Unused Pins
    4. 6.4 Device Functional Modes Configurations
  8. 7 Register Map
    1. 7.1 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Reference
      1. 8.1.1 Typical Application
        1. 8.1.1.1 Design Requirements
        2. 8.1.1.2 Detailed Design Procedure
        3. 8.1.1.3 Application Plots
    2. 8.2 Power Supply Recommendations
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

Figure 4-1 RHA Package40-Pin VQFNTop View
Table 4-1 Pin Functions
NAME NO. TYPE(1) DESCRIPTION
BIAS01 20 BYP If not using the multiplier, this pin can be left open. If using the multiplier, bypass this pin to GND with a 10nF capacitor for optimal noise performance.
BIAS23 31 BYP If not using the multiplier, this pin can be left open. If using the multiplier, bypass this pin to GND with a 10µF and 0.1µF capacitor for optimal noise performance.
CLKIN_N 7 I Differential clock input pair. Internal 50Ω termination at each pin. AC-couple with a capacitor appropriate to the input frequency (typically 0.1µF or smaller). If using single-ended, provide the input at CLKIN_N pin and terminate unused CLKIN_P with a series AC-coupling capacitor and 50Ω resistor to GND.
CLKIN_P 6
CLKOUT0_N 14 O Differential clock output pairs. Each pin is an open-collector output with internally integrated 50Ω resistor with programmable output swing. AC coupling is required. The pin expects 100Ω differential load or 50Ω load at each pin.
CLKOUT0_P 15
CLKOUT1_N 18
CLKOUT1_P 19
CLKOUT2_N 32
CLKOUT2_P 33
CLKOUT3_N 36
CLKOUT3_P 37
CS# 10 I SPI chip select. High impedance CMOS input. Accepts up to 3.3V. This pin requires 200Ω resistor in series.
DAP DAP GND Ground these pins.
GND 5,13,17,26,34,38
LOGICLKOUT0_N 27 O Differential Logic clock output pair. Selectable CML or LVDS format. LVDS format has programmable common-mode voltage. CML format requires external pull resistors.
LOGICLKOUT0_P 28
LOGISYSREFOUT_N / LOGICLKOUT1_N 23 O Differential Logic clock output pair. Selectable CML or LVDS format. LVDS format has programmable common-mode voltage. CML format requires external pull resistors.
LOGISYSREFOUT_P / LOGICLKOUT1_P 24
MUXOUT 1 O Multiplexed pin serial data readback and lock status of the multiplier.
SCK 8 I SPI clock. High impedance CMOS input. Accepts up to 3.3V. This pin requires 200Ω resistor in series.
SDI 9 I SPI data input. High impedance CMOS input. Accepts up to 3.3V. This pin requires 200Ω resistor in series.
SYSREFREQ_N 3 I Differential SYSREF request input for JESD204B/C support. Internal 50Ω termination at each pin. Supports AC and DC coupling which can directly accept a common mode voltage of 1.2V to 2V.
SYSREFREQ_P 2
SYSREFOUT0_N 11 O Differential SYSREF CML output pairs for JESD204B/C support. Supports AC and DC coupling with programmable common-mode voltage of 0.5V to 1.5V. The pin expects a 100Ω differential load.
SYSREFOUT0_P 12
SYSREFOUT1_N 21
SYSREFOUT1_P 22
SYSREFOUT2_N 29
SYSREFOUT2_P 30
SYSREFOUT3_N 39
SYSREFOUT3_P 40
VCC_CLKIN 4 PWR Connect to a 2.5V supply. Recommend a shunt high frequency capacitor (typically 0.1µF or smaller) closest to the pin in parallel with larger capacitors (typically 1µF and 10µF).
VCC_LOGICLK 25
VCC01 16
VCC23 35
(1) BYP = Bypass; GND = Ground; I = Input; O = Output; PWR = Power