SNAS850 December   2024 LMX1205

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Input
        1. 6.3.3.1 Clock Input Adjustable Delay
      4. 6.3.4 Clock Outputs
        1. 6.3.4.1 Clock Output Buffers
        2. 6.3.4.2 Clock Output Adjustable Delay
        3. 6.3.4.3 Clock MUX
        4. 6.3.4.4 Clock Divider
        5. 6.3.4.5 Clock Multiplier
          1. 6.3.4.5.1 General Information About the Clock Multiplier
          2. 6.3.4.5.2 State Machine Clock for the Clock Multiplier
            1. 6.3.4.5.2.1 State Machine Clock
          3. 6.3.4.5.3 Calibration for the Clock Multiplier
          4. 6.3.4.5.4 Lock Detect for the Clock Multiplier
      5. 6.3.5 LOGICLK Outputs
        1. 6.3.5.1 LOGICLK Output Format
        2. 6.3.5.2 LOGICLK Dividers
      6. 6.3.6 SYSREF
        1. 6.3.6.1 SYSREF Output Buffers
          1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.6.1.2 LOGISYSREF Output Buffer
          3. 6.3.6.1.3 SYSREF Frequency and Delay Generation
          4. 6.3.6.1.4 SYSREFREQ Pins and SYSREFREQ SPI Controlled Fields
            1. 6.3.6.1.4.1 SYSREFREQ Pins Common-Mode Voltage
            2. 6.3.6.1.4.2 SYSREFREQ Windowing Feature
              1. 6.3.6.1.4.2.1 General Procedure Flowchart for SYSREF Windowing Operation
              2. 6.3.6.1.4.2.2 Other Guidance For SYSREF Windowing
              3. 6.3.6.1.4.2.3 For Glitch-Free Output
              4. 6.3.6.1.4.2.4 If Using SYNC Feature
              5. 6.3.6.1.4.2.5 SYNC Feature
      7. 6.3.7 Power-Up Timing
      8. 6.3.8 Treatment of Unused Pins
    4. 6.4 Device Functional Modes Configurations
  8. 7 Register Map
    1. 7.1 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Reference
      1. 8.1.1 Typical Application
        1. 8.1.1.1 Design Requirements
        2. 8.1.1.2 Detailed Design Procedure
        3. 8.1.1.3 Application Plots
    2. 8.2 Power Supply Recommendations
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

2.4 V ≤ VCC ≤ 2.6 V, –40°C ≤ TA ≤ +85°C. Typical values are at VCC = 2.5 V, 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current Consumption
ICC Supply Current (1) Powered up, all Clock outputs and SYSREFs on 1130 mA
Powered up, all Clock outputs on, all SYSREF off 700
Powered up, all Clock outputs and SYSREF off 370
Powered down 13.5
IADD Additive output current OUTx_PWR = 6 64 mA
Multiplier current Divide, CLK_DIV = 8 60
Multiplier, CLK_MULT = x8 360
SYSREF current Running at 100MHz
Generation mode, all outputs on		 425
LOGICLK current LOGICLK enabled with LOGISYSREF 85
SYSREF
fSYSREF SYSREF output frequency Generator mode Generator mode 200 MHz
fSYSREF SYSREF output frequency Repeater mode Repeater mode 100 MHz
TSYNC Pulse width required for SYNC signal Tsync = 6xT of fCLKIN , fCLKIN = 6GHz 1000 ps
Δt SYSREF delay step size Δt = SYSREF_DLY_DIV/ (508 x fCLKIN), fCLKIN = 12.8GHz 3 ps
tRISE Rise time (20% to 80%) SYSREFOUT 45 ps
LOGISYSREFOUT CML 65 ps
LVDS 120 175 ps
tFALL Fall time (20% to 80%) SYSREFOUT 45 ps
LOGISYSREFOUT CML 65 ps
LVDS 120 175 ps
VODDIFF Differential pk-pk output voltage SYSREFOUT,  SYSREFx_PWR = 4, SYSREFx_VCM = 10 0.9 Vpp
LOGISYSREFOUT CML 0.9 Vpp
LVDS 0.7 Vpp
VSYSREFCM Common mode voltage SYSREFOUT CML
SYSREFx_VCM=41, 100Ω Differential Load		 1.35 1.5 1.65 V
CML
SYSREFx_VCM=4,
100Ω Differential Load		 0.45 0.5 0.55 V
LOGISYSREFOUT LVDS
100Ω Differential Load		 0.75 1.4 V
SYSREFREQ Pins
VSYSREFIN Differential pk-pk Voltage input range AC differential voltage 0.8 2 Vpp
VSYSREFIN Single-ended voltage input range AC Coupled to SYSREFREQ_P;
SYSREFREQ_N AC coupled to GND		 AC Coupled to SYSREFREQ_P;
SYSREFREQ_N AC coupled to GND		 0.6 1.7 Vpp
VCM Input common mode voltage Differential 100Ω Termination, DC coupled
Set externally		 1.2 1.3 2 V
Clock Input
fIN Input frequency 0.3 12.8 GHz
PIN Input power Single-ended power at CLKIN_P or CLKIN_N 0 10 dBm
ϕIN Input delay range 60 ps
ΔIN Input delay programmable step 1.1 ps
Clock Outputs
fOUT Output frequency Divide-by-2 0.15 6.4 GHz
fOUT Output frequency Buffer Mode 0.3 12.8
fOUT Output frequency Multiplier Mode 6.4 12.8
fOUT Output frequency LOGICLK output 1 800 MHz
tCAL Calibration-time Multiplier calibration time fIN = 6.4GHz; x2
fSMCLK = 28 MHz		 750 µs
pOUT Output power Single-Ended fCLKLOUT= 6GHz
OUTx_PWR = 6		 4.8 dBm
tRISE Rise time (20% to 80%) fCLKOUT = 300 MHz 45 ps
tFALL Fall time (20% to 80%) fCLKOUT = 300 MHz 45 ps
VLOGICLKCM Common mode voltage LOGICLKOUT0 LVDS 0.7 1.2 1.5 V
ϕIN Output delay range 55 ps
ΔϕIN Output delay programmable step size 0.9 ps
Propagation Delay and Skew
| tSKEW | Magnitude of skew between outputs CLKOUTx to CLKOUTy, not LOGICLK 1 10 ps
| tSKEW | Magnitude of skew between CLKOUT and SYSREF SYSREF Continuous/Pulse Mode SYSREF delay gen bypass 60 ps
| tSKEW | Magnitude of skew between CLKOUT and SYSREF SYSREF Repeater retime Mode SYSREF delay gen bypass 100 ps
ΔtDLY/ΔT Propagation delay variation over temperature Buffer mode 0.02 0.06 0.10 ps/℃
tDLY Propagation delay Buffer mode TA = 25℃ 165 ps
Divider Mode 175 ps
Multiplier Mode 155 ps
tDLY Propagation delay SYSREF out Repeater mode TA = 25℃ 185 ps
Noise, Jitter, and Spurs
σCLKOUT CLKOUT Additive jitter Additive Jitter. 100Hz to 100MHz integration bandwidth. Buffer Mode 10 fs, rms
x2 Multiplier 21
x3 Multiplier 25
x4 Multiplier 33
x5 Multiplier 35
x6 Multiplier 48
x7 Multiplier 50
x8 Multiplier 60
1/fCLKOUT 1/f flicker noise Slew Rate > 8 V/ns, fCLK=6GHz Buffer Mode –154 dBc/Hz
NFCLKOUT Noise Floor fOUT = 6.4GHz; fOffset =100MHz Buffer Mode –159 dBc/Hz
Divide-by-2 –158.5
Multiplier (x2,x3,x4,x5,x6,x7,x8) –159.5
NFLOGICLK Noise Floor LOGICLK output, 300 MHz CML –150.5 dBc/Hz
LVDS –151.5
H2 Second harmonic Buffer Mode
fOUT=6.4GHz		 Differential –25 dBc
Single-Ended –15
Divide by 2
fOUT=6.4GHz		 Single-Ended –17
H1/M Input clock leakage spur fOUT = 12GHz (differential) x2 (fSPUR = 6GHz) –40 dBc
fOUT = 12GHz (differential) x3 (fSPUR = 4GHz) –40
fOUT = 12GHz (differential) x4 (fSPUR = 3GHz) –50
fOUT = 12GHz (differential) x6  (fSPUR = 2GHz) -50
fOUT = 10GHz (differential) x5 (fSPUR = 2GHz) -50
fOUT = 10.5GHz (differential) x7 (fSPUR = 1.5GHz) -52
fOUT = 12GHz (differential) x8  (fSPUR = 1.5GHz) -55
Pcrosstalk LOGICLK to CLKOUT fSPUR = 300MHz (differential) –70 dBc
SYSREFOUT to CLKOUT Generation mode -70 dBc
repeater mode -65 dBc
PLEAK CLKIN to CLKOUT Leakage in Buffer Mode Differential Input -70 dBc
Digital Interface (SCK, SDI, CS#, MUXOUT)
VIH High-level input voltage SCK, SDI, CS# 1.4 3.3 V
VIL Low-level input voltage 0 0.4
VOH High-level output voltage IOH = 5mA 1.4 Vcc
IOH = 0.1mA 2.2 Vcc
VOL Low-level output voltage IOL = 5mA 0.45
IIH High-level input current –42 42 μA
IIL Low-level input current –25 25
(1) Unless Otherwise Stated, fCLKIN=6.4GHz, CLK_MUX=Buffer, All clocks on with OUTx_PWR=6, SYSREFREQ_MODE=1