JAJSSL4A December   2023  – September 2024 LMX1214

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power-On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
      4. 6.3.4 AUXCLK Output
        1. 6.3.4.1 AUXCLKOUT Output Format
        2. 6.3.4.2 AUXCLK_DIV_PRE and AUXCLK_DIV Dividers
      5. 6.3.5 SYNC Input Pins
        1. 6.3.5.1 SYNC Pins Common-Mode Voltage
        2. 6.3.5.2 Windowing Feature
    4. 6.4 Device Functional Modes Configurations
      1. 6.4.1 Pin Mode Control
  8. 7 Register Map
    1. 7.1 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 SYNC Input Configuration
      2. 8.1.2 Treatment of Unused Pins
      3. 8.1.3 Current Consumption
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Plots
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions



Figure 4-1 RHA0040C Package40-Pin VQFNTop View
Table 4-1 Pin Functions
NO. NAME TYPE(1) DESCRIPTION
1 MUXOUT O SPI readback output (SDO).
2 SYNC_P I Differential synchronization input. Internal 100-Ω differential termination AC-coupled to GND with a 10-pf capacitor. Supports AC and DC coupling which can directly accept a common mode voltage of 1.2 V to 2 V.
3 SYNC_N
4 VCC_CLKIN PWR Connect to a 2.5-V supply. Recommend a shunt RF wideband capacitor (typically 0.1 µF or smaller) close to the pin in parallel with larger capacitors (typically 1 µF and 10 µF). Large capacitors can be placed bit further away from the pin.
5 GND GND Ground these pins.
6 CLKIN_P I Differential reference input clock. Internal 100-Ω differential termination. AC-couple with a capacitor appropriate to the input frequency (typically 0.1 µF or smaller). If using single-ended, terminate unused pin with 50-Ω resistor AC-coupled to ground.
7 CLKIN_N
8 SCK I SPI clock. High impedance CMOS input. Accepts up to 3.3 V.
9 SDI I SPI data input. High impedance CMOS input. Accepts up to 3.3 V.
10 CS# I SPI chip select. High impedance CMOS input. Accepts up to 3.3 V.
11 NC — Not connected
12 VCC01 PWR Connect to a 2.5-V supply. Recommend a shunt RF wideband capacitor (typically 0.1 µF or smaller) close to the pin in parallel with larger capacitors (typically 1 µF and 10 µF). Large capacitors can be placed bit further away from the pin.
13 GND GND Ground this pin
14 CLKOUT0_N O Differential clock output pairs. Each pin is an open-collector output with internally integrated 50-Ω resistor with programmable output swing. AC coupling required.
15 CLKOUT0_P
16 VCC01 PWR Connect to a 2.5-V supply. Recommend a shunt RF wideband capacitor (typically 0.1 µF or smaller) close to the pin in parallel with larger capacitors (typically 1 µF and 10 µF). Large capacitors can be placed bit further away from the pin.
17 GND GND Ground this pin
18 CLKOUT1_N O Differential clock output pairs. Each pin is an open-collector output with internally integrated 50-Ω resistor with programmable output swing. AC coupling required.
19 CLKOUT1_P
20 GND GND Ground this pin
21 CLK0_EN I CLKOUT0 output enable pin
22 CLK1_EN I CLKOUT1 output enable pin
23 DIVSEL1 I Main clock out divider value 2, 3, and 4 selection control pins
24 DIVSEL0
25 VCC_AUXCLK PWR Connect to a 2.5-V supply. Recommend a shunt RF wideband capacitor (typically 0.1 µF or smaller) close to the pin in parallel with larger capacitors (typically 1 µF and 10 µF). Large capacitors can be placed bit further away from the pin.
26 GND GND Ground this pin
27 AUXCLKOUT_N O Differential clock output pair. Selectable CML, or LVDS format. Programmable common-mode voltage.
28 AUXCLKOUT_P
29 MUXSEL I Clock out Bypass or Divider path MUX selection
30 CLK23_EN I CLKOUT2 & CLKOUT3 output enable pin
31 GND GND Ground this pin
32 CLKOUT2_N O Differential clock output pairs. Each pin is an open-collector output with internally integrated 50-Ω resistor with programmable output swing. AC coupling required.
33 CLKOUT2_P
34 GND GND Ground this pin
35 VCC23 PWR Connect to a 2.5-V supply. Recommend a shunt RF wideband capacitor (typically 0.1 µF or smaller) close to the pin in parallel with larger capacitors (typically 1 µF and 10 µF). Large capacitors can be placed bit further away from the pin.
36 CLKOUT3_N O Differential clock output pairs. Each pin is an open-collector output with internally integrated 50-Ω resistor with programmable output swing. AC coupling required.
37 CLKOUT3_P
38 GND GND Ground this pin
39 VCC23 PWR Connect to a 2.5-V supply. Recommend a shunt RF wideband capacitor (typically 0.1 µF or smaller) close to the pin in parallel with larger capacitors (typically 1 µF and 10 µF). Large capacitors can be placed bit further away from the pin.
40 NC — Not connected
GND DAP GND Ground this pin
(1) I = Input; O = Output; GND = Ground; PWR = Power